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9 Commits

Author SHA1 Message Date
Evan Cheng 1355bbdd11 Be careful about scheduling nodes above previous calls. It increase usages of 
more callee-saved registers and introduce copies. Only allows it if scheduling
a node above calls would end up lessen register pressure.

Call operands also has added ABI restrictions for register allocation, so be
extra careful with hoisting them above calls.

rdar://9329627

llvm-svn: 130245
 2011-04-26 21:31:35 +00:00
Jakob Stoklund Olesen 100f53fd25 Fix Thumb and Thumb2 tests to be register allocator independent. 
llvm-svn: 128690
 2011-03-31 23:31:50 +00:00
Jim Grosbach 66c681a644 Now that register allocation properly considers reserved regs, simplify the 
ARM register class allocation order functions to take advantage of that.

llvm-svn: 112841
 2010-09-02 18:14:29 +00:00
Bob Wilson bb57896f8e Fix test to appease the buildbots. 
llvm-svn: 108334
 2010-07-14 16:43:47 +00:00
Evan Cheng cf9e8a987f Fix an inverted condition. 
llvm-svn: 106330
 2010-06-18 22:17:13 +00:00
Evan Cheng f128bdcb55 Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. 
llvm-svn: 106091
 2010-06-16 07:35:02 +00:00
Dan Gohman 2ad68de4aa Fix a bug which prevented tail merging of return instructions in 
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and
test/CodeGen/ARM/ifcvt2.ll for details.

The fix is to change HashEndOfMBB to hash at most one instruction,
instead of trying to apply heuristics about when it will be profitable to
consider more than one instruction. The regular tail-merging heuristics
are already prepared to handle the same cases, and they're more precise.

Also, make test/CodeGen/ARM/ifcvt5.ll and
test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they
continue to test what they're intended to test.

And, this eliminates the problem in
test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from
PR5204. Update it accordingly.

llvm-svn: 102907
 2010-05-03 14:35:47 +00:00
Bob Wilson 298a83ecfe Stop using the old pre-UAL syntax for LDM/STM instruction suffixes. 
This does not move entirely to UAL syntax, since the default "increment after"
suffix is empty but we still use "IA" for that.

llvm-svn: 98635
 2010-03-16 16:19:07 +00:00
Sandeep Patel 3f23601b00 Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng. 
llvm-svn: 84212
 2009-10-15 22:25:32 +00:00