Commit Graph

311274 Commits

Author SHA1 Message Date
Alex Langford 0ca4f84f2f [build.py] Allow clang-cl to build files starting with '/U'
Summary:
clang-cl tries to match cl's interface, and treats /U as "Removes a
predefined macro" as cl does. When you feed clang-cl a file that begins with
'/U' (e.g. /Users/xiaobai/foo.c), clang-cl will emit a warning and in some cases
an error, like so:

clang-9: warning: '/Users/xiaobai/foo.c' treated as the '/U' option [-Wslash-u-filename]
clang-9: note: Use '--' to treat subsequent arguments as filenames
clang-9: error: no input files

If you're using clang-cl, make sure '--' is passed before the source file.

Differential Revision: https://reviews.llvm.org/D58860

llvm-svn: 355341
2019-03-04 21:36:49 +00:00
Shoaib Meenai 5be71faf4b [build] Rename clang-headers to clang-resource-headers
Summary:
The current install-clang-headers target installs clang's resource
directory headers. This is different from the install-llvm-headers
target, which installs LLVM's API headers. We want to introduce the
corresponding target to clang, and the natural name for that new target
would be install-clang-headers. Rename the existing target to
install-clang-resource-headers to free up the install-clang-headers name
for the new target, following the discussion on cfe-dev [1].

I didn't find any bots on zorg referencing install-clang-headers. I'll
send out another PSA to cfe-dev to accompany this rename.

[1] http://lists.llvm.org/pipermail/cfe-dev/2019-February/061365.html

Reviewers: beanz, phosek, tstellar, rnk, dim, serge-sans-paille

Subscribers: mgorny, javed.absar, jdoerfert, #sanitizers, openmp-commits, lldb-commits, cfe-commits, llvm-commits

Tags: #clang, #sanitizers, #lldb, #openmp, #llvm

Differential Revision: https://reviews.llvm.org/D58791

llvm-svn: 355340
2019-03-04 21:19:53 +00:00
Jessica Paquette 0632e12f89 [GlobalISel][AArch64] Legalize vector G_SELECT
Just scalarize it, and add a test showing it works.

Differential Revision: https://reviews.llvm.org/D58747

llvm-svn: 355339
2019-03-04 21:12:46 +00:00
Evgeniy Stepanov e800a32b93 Fix wrong enum value in switch.
llvm-svn: 355338
2019-03-04 21:00:28 +00:00
Sanjay Patel 6e32b46b1d [ConstantHoisting] avoid hang/crash from unreachable blocks (PR40930)
I'm not too familiar with this pass, so there might be a better
solution, but this appears to fix the degenerate:
PR40930
PR40931
PR40932
PR40934
...without affecting any real-world code.

As we've seen in several other passes, when we have unreachable blocks,
they can contain semi-bogus IR and/or cause unexpected conditions. We
would not typically expect these patterns to make it this far, but we
have to guard against them anyway.

llvm-svn: 355337
2019-03-04 20:57:14 +00:00
Louis Dionne fc778fa2c5 [libc++] Remove old CMake workaround
We haven't had any complaints so far, and I don't think anybody builds
libc++ from source for that old platform anymore.

llvm-svn: 355336
2019-03-04 20:52:14 +00:00
Eric Fiselier 8b73ab29c3 Install GCC 5 on buildbots to replace GCC 4.9.
LLVM is dropping support for GCC 4.9. This patch adds
a GCC 5 installation to the buildbot image so we can upgrade
the 4.9 bot to GCC 5.

As a temporary workaround until zorg updates, we install GCC 5
as GCC 4.9.

llvm-svn: 355334
2019-03-04 20:49:18 +00:00
Manman Ren 394d4ccf69 Order File Instrumentation: add clang support for -forder-file-instrumentation
When -forder-file-instrumentation is on, we pass llvm flag to enable the order file instrumentation pass.

https://reviews.llvm.org/D58751

llvm-svn: 355333
2019-03-04 20:30:30 +00:00
Shafik Yaghmour 9adbbcb7cd [ASTImporter] Handle built-in when importing SourceLocation and FileID
Summary:
Currently when we see a built-in we try and import the include location. Instead what we do now is find the buffer like we do for the invalid case and copy that over to the to context.

Differential Revision: https://reviews.llvm.org/D58743

llvm-svn: 355332
2019-03-04 20:25:54 +00:00
Rong Xu a4a09b2398 [PGO] Clang part of change for context-sensitive PGO (part1)
Part 1 of CSPGO change in Clang. This includes changes in clang options
and calls to llvm PassManager. Tests will be committed in part2.
This change needs the PassManager change in llvm.

Differential Revision: https://reviews.llvm.org/D54176

llvm-svn: 355331
2019-03-04 20:21:31 +00:00
Rong Xu db29a3a438 [PGO] Context sensitive PGO (part 3)
Part 3 of CSPGO changes (mostly related to PassMananger).

Differential Revision: https://reviews.llvm.org/D54175

llvm-svn: 355330
2019-03-04 20:21:27 +00:00
Zachary Turner bb4d4e2d76 Fix Windows build after UserIDResolver patch.
That patch added a function to HostInfo that returns an instance
of UserIDResolver, but this function was unimplemented on Windows,
leading to linker errors.  For now, just return a dummy implementation
that doesn't resolve user ids to get the build green.

llvm-svn: 355329
2019-03-04 19:57:04 +00:00
Nikita Popov 8670faf939 [InstCombine] Add tests for add nsw + sadd.with.overflow; NFC
Baseline tests for D58881, which fixes part of PR38146.

Patch by Dan Robertson.

llvm-svn: 355328
2019-03-04 19:35:46 +00:00
Craig Topper 2729a91825 [Subtarget] Follow up to r355167, add another set of curly braces to FeatureBitArray initialization to satisfy older versions of clang.
Apparently older versions of clang like 3.6 require an extra set of curly braces around std::array initializations. I'm told the C++ language was changed regarding this by CWG 1270.

llvm-svn: 355327
2019-03-04 19:23:37 +00:00
Amara Emerson 8acb0d9c82 Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1."
The code to materialize a mask from a constant pool load tried to use a 128 bit
LDR to load a 64 bit constant pool entry, which was 8 byte aligned. This resulted
in a link failure in the NEON tests in the test suite since the LDR address was
unaligned. This change fixes that to instead emit a 64 bit LDR if the entry is
64 bit, before converting back to a 128 bit register for the TBL.

llvm-svn: 355326
2019-03-04 19:16:00 +00:00
Nirav Dave 05e2335076 [MC] Teach ELFObjectWriter that parse-time variables do not appear in
symbol table.

llvm-svn: 355325
2019-03-04 19:12:56 +00:00
Craig Topper 509a8a3cf1 [DAGCombiner][X86][SystemZ][AArch64] Combine some cases of (bitcast (build_vector constants)) between legalize types and legalize dag.
This patch enables combining integer bitcasts of integer build vectors when the new scalar type is legal. I've avoided floating point because the implementation bitcasts float to int along the way and we would need to check the intermediate types for legality

Differential Revision: https://reviews.llvm.org/D58884

llvm-svn: 355324
2019-03-04 19:12:16 +00:00
Pavel Labath aa51e6a683 Refactor user/group name resolving code
Summary:
This creates an abstract base class called "UserIDResolver", which can
be implemented to provide user/group ID resolution capabilities for
various objects. Posix host implement a PosixUserIDResolver, which does
that using posix apis (getpwuid and friends).  PlatformGDBRemote
forwards queries over the gdb-remote link, etc. ProcessInstanceInfo
class is refactored to make use of this interface instead of taking a
platform pointer as an argument. The base resolver class already
implements caching and thread-safety, so implementations don't have to
worry about that.

The main motivating factor for this was to remove external dependencies
from the ProcessInstanceInfo class (so it can be put next to
ProcessLaunchInfo and friends), but it has other benefits too:
- ability to test the user name caching code
- ability to test ProcessInstanceInfo dumping code
- consistent interface for user/group resolution between Platform and
  Host classes.

Reviewers: zturner, clayborg, jingham

Subscribers: mgorny, lldb-commits

Differential Revision: https://reviews.llvm.org/D58167

llvm-svn: 355323
2019-03-04 18:48:00 +00:00
Erich Keane ac8d1b7017 Enable _rotl, _lrotl, _rotr, _lrotr on all platforms.
The above builtins are currently implemented for MSVC mode, however GCC
also implements these.  This patch enables them for all platforms.

Additionally, this corrects the type for these builtins to always be
'long int' to match the specification in the Intel Intrinsics Guide.

Change-Id: Ida34be98078709584ef5136c8761783435ec02b1
llvm-svn: 355322
2019-03-04 18:47:21 +00:00
Wouter van Oortmerssen f3feb6adb9 [WebAssembly] Add support for data sections in the assembler.
Summary:
This is quite minimal so far, introduce them with .section,
fill them with .int8 or .asciz, end with .size

Reviewers: dschuff, sbc100, aheejin

Subscribers: jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58660

llvm-svn: 355321
2019-03-04 17:18:04 +00:00
Michal Gorny de11105d2e [lldb] [test] Mark failing tests XFAIL on NetBSD
Add a convenience 'expectedFailureNetBSD' decorator and mark all tests
currently failing on NetBSD with it.  Also skip a few tests that hang
the test suite.  This should establish a baseline for the test suite
and get us closer to enabling tests on buildbot.  This will help us
catch regressions while we still have a lot of work to do to get tests
working.

It seems that there are also some flaky tests.  I am going to address
them later on.

Differential Revision: https://reviews.llvm.org/D58527

llvm-svn: 355320
2019-03-04 16:54:06 +00:00
Kamil Rytarowski 502ba11583 Revert duplicate check for DragonFly BSD
Summary: Revert duplicate check for DragonFly BSD

Submitted by tuxillo.

Reviewers: krytarowski

Reviewed By: krytarowski

Subscribers: mgorny, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58907

llvm-svn: 355319
2019-03-04 15:51:02 +00:00
Louis Dionne 21450545d1 [libc++] decoupling Freestanding atomic<T> from libatomic.a
This patch introduces non-lockfree atomics that do not require using
an external libatomic. This work is done with the long-term goal of
allowing the use of <atomic> in freestanding environments.

Thanks to Olivier Giroux for the patch.
Differential Revision: https://reviews.llvm.org/D56913

llvm-svn: 355318
2019-03-04 15:26:27 +00:00
Erich Keane 881e83d8b9 Give builtins and alloc/dealloc operators the default calling convention.
On SPIR targets, the default calling convention is SpirFunction.
However, operator new/delete and builtins were being created with CC_C.
The result is indirect references to new/delete (or builtins that are permitted
to be called indirectly have a mismatched type, as well as questionable codegen
in some cases.

This patch sets both to the default calling convention, so that it
properly matches the calling convention of the target.

Differential Revision: https://reviews.llvm.org/D58844

Change-Id: I52065bb00bc2655945caea8f29c409ba1e0ac24a
llvm-svn: 355317
2019-03-04 14:54:52 +00:00
Simon Pilgrim eeb1144d27 [X86] Regenerate illegal type load test with non-undef load address.
This would be affected by an upcoming patch without undoing some of the bugpoint reduction.

llvm-svn: 355316
2019-03-04 14:49:02 +00:00
Kamil Rytarowski 0c5b6ede2f Unbreak shared library linkage on DragonFlyBSD.
Patch submitted by rimvydas.

Reviewers: llvm-commits, krytarowski, mgorny

Reviewed By: krytarowski, mgorny

Subscribers: mgorny

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D35125

llvm-svn: 355315
2019-03-04 14:36:43 +00:00
Andrea Di Biagio 3437142aad [MCA] Remove unused methods. NFC
llvm-svn: 355314
2019-03-04 13:34:56 +00:00
Dmitry Preobrazhensky 6023d5990d [AMDGPU][MC] Enable lds_direct operand for v_readfirstlane_b32, v_readlane_b32 and v_writelane_b32
See bug 40662: https://bugs.llvm.org/show_bug.cgi?id=40662

Reviewers: artem.tamazov, arsenm, rampitec

Differential Revision: https://reviews.llvm.org/D58713

llvm-svn: 355312
2019-03-04 12:48:32 +00:00
Andrea Di Biagio 9735d9011a [MCA] Correctly initialize struct SummaryView::BackPressureInfo.
This should appease the buildbots.

llvm-svn: 355309
2019-03-04 12:23:05 +00:00
Andrea Di Biagio be3281a281 [MCA] Highlight kernel bottlenecks in the summary view.
This patch adds a new flag named -bottleneck-analysis to print out information
about throughput bottlenecks.

MCA knows how to identify and classify dynamic dispatch stalls. However, it
doesn't know how to analyze and highlight kernel bottlenecks.  The goal of this
patch is to teach MCA how to correlate increases in backend pressure to backend
stalls (and therefore, the loss of throughput).

From a Scheduler point of view, backend pressure is a function of the scheduler
buffer usage (i.e. how the number of uOps in the scheduler buffers changes over
time). Backend pressure increases (or decreases) when there is a mismatch
between the number of opcodes dispatched, and the number of opcodes issued in
the same cycle.  Since buffer resources are limited, continuous increases in
backend pressure would eventually leads to dispatch stalls. So, there is a
strong correlation between dispatch stalls, and how backpressure changed over
time.

This patch teaches how to identify situations where backend pressure increases
due to:
 - unavailable pipeline resources.
 - data dependencies.

Data dependencies may delay execution of instructions and therefore increase the
time that uOps have to spend in the scheduler buffers. That often translates to
an increase in backend pressure which may eventually lead to a bottleneck.
Contention on pipeline resources may also delay execution of instructions, and
lead to a temporary increase in backend pressure.

Internally, the Scheduler classifies instructions based on whether register /
memory operands are available or not.

An instruction is marked as "ready to execute" only if data dependencies are
fully resolved.
Every cycle, the Scheduler attempts to execute all instructions that are ready
to execute. If an instruction cannot execute because of unavailable pipeline
resources, then the Scheduler internally updates a BusyResourceUnits mask with
the ID of each unavailable resource.

ExecuteStage is responsible for tracking changes in backend pressure. If backend
pressure increases during a cycle because of contention on pipeline resources,
then ExecuteStage sends a "backend pressure" event to the listeners.
That event would contain information about instructions delayed by resource
pressure, as well as the BusyResourceUnits mask.

Note that ExecuteStage also knows how to identify situations where backpressure
increased because of delays introduced by data dependencies.

The SummaryView observes "backend pressure" events and prints out a "bottleneck
report".

Example of bottleneck report:

```
Cycles with backend pressure increase [ 99.89% ]
Throughput Bottlenecks:
  Resource Pressure       [ 0.00% ]
  Data Dependencies:      [ 99.89% ]
   - Register Dependencies [ 0.00% ]
   - Memory Dependencies   [ 99.89% ]
```

A bottleneck report is printed out only if increases in backend pressure
eventually caused backend stalls.

About the time complexity:

Time complexity is linear in the number of instructions in the
Scheduler::PendingSet.

The average slowdown tends to be in the range of ~5-6%.
For memory intensive kernels, the slowdown can be significant if flag
-noalias=false is specified. In the worst case scenario I have observed a
slowdown of ~30% when flag -noalias=false was specified.

We can definitely recover part of that slowdown if we optimize class LSUnit (by
doing extra bookkeeping to speedup queries). For now, this new analysis is
disabled by default, and it can be enabled via flag -bottleneck-analysis. Users
of MCA as a library can enable the generation of pressure events through the
constructor of ExecuteStage.

This patch partially addresses https://bugs.llvm.org/show_bug.cgi?id=37494

Differential Revision: https://reviews.llvm.org/D58728

llvm-svn: 355308
2019-03-04 11:52:34 +00:00
Jeremy Morse 09d8ea5282 [X86] Avoid codegen changes when DBG_VALUE appears between lowered selects
X86TargetLowering::EmitLoweredSelect presently detects sequences of CMOV pseudo
instructions without accounting for debug intrinsics. This leads to different
codegen with and without option -g, if a DBG_VALUE instruction lands in the
middle of several lowered selects.

Work around this by skipping over debug instructions when looking for CMOV
sequences, and sinking those debug insts into the EmitLoweredSelect sunk block.
This might slightly shift where variables appear in the instruction sequence,
but won't re-order assignments.

Differential Revision: https://reviews.llvm.org/D58672

llvm-svn: 355307
2019-03-04 10:56:02 +00:00
Alexey Lapshin ded118079b [LLD] add test for line number info related to differrent .text sections
There is a bug for llvm-objdump which incorrectly reported line number
   info for object file if several .text sections presented.
   https://bugs.llvm.org/show_bug.cgi?id=40703 .
   This patch adds test for the same situation.

   Differential revision: https://reviews.llvm.org/D58357

llvm-svn: 355306
2019-03-04 10:42:54 +00:00
Oliver Stannard 181afc7f3b [ARM] Fix selection of VLDR.16 instruction with imm offset
The isScaledConstantInRange function takes upper and lower bounds which are
checked after dividing by the scale, so the bounds checks for half, single and
double precision should all be the same. Previously, we had wrong bounds checks
for half precision, so selected an immediate the instructions can't actually
represent.

Differential revision: https://reviews.llvm.org/D58822

llvm-svn: 355305
2019-03-04 09:17:38 +00:00
Jonas Hahnfeld 65a401f6a9 [AArch64/ARM] Fix two compiler warnings in InstructionSelector, NFCI
1) GCC complains that KnownValid is set but not used.
2) In ARMInstructionSelector::selectGlobal() the code is mixing "enumeral
   and non-enumeral type in conditional expression". Solve this by casting
   to unsigned which is the final type anyway.

Differential Revision: https://reviews.llvm.org/D58834

llvm-svn: 355304
2019-03-04 08:51:32 +00:00
Eugene Leviant daea28ab64 [DebugInfo] Construct nested types on behalf of owner CU
Differential revision: https://reviews.llvm.org/D58786

llvm-svn: 355303
2019-03-04 07:15:36 +00:00
Michal Gorny 2d8be64401 [llvm] [Support] Revert "Reimplement getMainExecutable() using sysctl on NetBSD"
This apparently does not work reliably after all (non-reentrant?)
and causes test failures such as:

http://lab.llvm.org:8011/builders/netbsd-amd64/builds/19254/steps/run%20unit%20tests/logs/FAIL%3A%20libc%2B%2B%3A%3Asize.pass.cpp

llvm-svn: 355302
2019-03-04 04:53:50 +00:00
Davide Italiano 672bec223d [InstCombine] Mark debug values as unavailable after DCE.
Fixes PR40838.

llvm-svn: 355301
2019-03-04 04:38:58 +00:00
Craig Topper 69abb15b81 [SubtargetFeatures] Add operator< for comparing SubtargetInfoKV objects. NFCI
Use instead of passing a lambda to std::is_sorted. This is more consistent with SubtargetFeatureKV.

llvm-svn: 355300
2019-03-04 04:26:31 +00:00
Craig Topper b306ef12f0 [SubtargetFeatures] Don't call ApplyFeatureFlag if the feature name is '+help'
Just print the help and stop. Otherwise we'll print a message about it not being a real feature name after printing the help text.

llvm-svn: 355299
2019-03-04 02:02:24 +00:00
Craig Topper a761f9f407 [SubtargetFeatuers] Simplify the code used to imply features from CPU name.
If we make SetImpliedBits OR features outside of its loop, we can reuse it for the first round of implying features for CPUs.

llvm-svn: 355298
2019-03-04 02:02:22 +00:00
Kristof Umann 088b1c9cdc [analyzer] Enable subcheckers to possess checker options
Under the term "subchecker", I mean checkers that do not have a checker class on
their own, like unix.MallocChecker to unix.DynamicMemoryModeling.

Since a checker object was required in order to retrieve checker options,
subcheckers couldn't possess options on their own.

This patch is also an excuse to change the argument order of getChecker*Option,
it always bothered me, now it resembles the actual command line argument
(checkername:option=value).

Differential Revision: https://reviews.llvm.org/D57579

llvm-svn: 355297
2019-03-04 00:28:16 +00:00
Heejin Ahn 195a62e9ae [WebAssembly] Delete ThrowUnwindDest map from WasmEHFuncInfo
Summary:
Before when we implemented the first EH proposal, 'catch <tag>'
instruction may not catch an exception so there were multiple EH pads an
exception can unwind to. That means a BB could have multiple EH pad
successors.

Now after we switched to the new proposal, every 'catch' instruction
catches an exception, and there is only one catchpad per catchswitch, so
we at most have one EH pad successor, making `ThrowUnwindDest` map in
`WasmEHInfo` unnecessary.

Keeping `ThrowUnwindDest` map in `WasmEHInfo` has its own problems,
because other optimization passes can split a BB that contains possibly
throwing calls (previously invokes), and we have to update the map every
time that happens, which is not easy for common CodeGen passes.

This also correctly updates successor info in LateEHPrepare when we add
a rethrow instruction.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D58486

llvm-svn: 355296
2019-03-03 22:35:56 +00:00
Craig Topper e9e4a0f5b4 [X86] Regenerate test to get the full FP operands printed. NFC
Missed when I updated the printer to print implicit %st operand on binops.

llvm-svn: 355295
2019-03-03 20:28:52 +00:00
Duncan P. N. Exon Smith fae03d8add Modules: Document that ReadASTCore exits its final loop via `return`, NFC
The final loop never breaks.  Document that by following it with
llvm_unreachable.

llvm-svn: 355294
2019-03-03 20:17:53 +00:00
Sanjay Patel e076491759 [InstCombine] remove stale FIXME comment from test; NFC
llvm-svn: 355293
2019-03-03 19:08:54 +00:00
Sanjay Patel 2a70703770 [ValueTracking] do not try to peek through bitcasts in computeKnownBitsFromAssume()
There are no tests for this case, and I'm not sure how it could ever work,
so I'm just removing this option from the matcher. This should fix PR40940:
https://bugs.llvm.org/show_bug.cgi?id=40940

llvm-svn: 355292
2019-03-03 18:59:33 +00:00
Amaury Sechet d341a94261 Add extra ops in add to sub transform test in order to enforce proper operand ordering. NFC
llvm-svn: 355291
2019-03-03 15:11:13 +00:00
Fangrui Song 5fa53d1593 [DemandedBits] Remove some redundancy in the work list
InputIsKnownDead check is shared by all operands. Compute it once.

For non-integer instructions, use Visited.insert(I).second to replace a
find() and an insert().

llvm-svn: 355290
2019-03-03 14:50:01 +00:00
Simon Pilgrim e48be5d698 Remove unused variable. NFCI.
llvm-svn: 355289
2019-03-03 14:23:07 +00:00
Simon Pilgrim d8e91a54c0 [X86] getShuffleScalarElt - peek through insert/extract subvector nodes.
llvm-svn: 355288
2019-03-03 14:11:05 +00:00