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103 Commits

Author SHA1 Message Date
Kai Nacke 13673ac704 [mips] Add more Octeon cnMips instructions 
Adds the instructions ext/ext32/cins/cins32.
It also changes pop/dpop to accept the two operand version and
adds a simple pattern to generate baddu.
Tests for the two operand versions (including baddu/dmul/dpop/pop)
and the code generation pattern for baddu are included.

Reviewed by: Daniel.Sanders@imgtec.com

llvm-svn: 205449
 2014-04-02 18:40:43 +00:00
Kai Nacke af47f60f83 [mips] Add Octeon cnMips instructions mtmX and mtpX 
Adds the Octeon cnMips instructions "load multiplier register MPLx" and "load product register Px".
Includes tests.

Reviews by: Daniel.Sanders@imgtec.com

llvm-svn: 205343
 2014-04-01 18:35:26 +00:00
Kai Nacke 93fe5e810d [MIPS] Add cpu octeon and some instructions 
The Octeon cpu from Cavium Networks is mips64r2 based and has an extended
instruction set. In order to utilize this with LLVM, a new cpu feature "octeon"
and a subtarget feature "cnmips" is added. A small set of new instructions
(baddu, dmul, pop, dpop, seq, sne) is also added. LLVM generates dmul, pop and
dpop instructions with option -mcpu=octeon or -mattr=+cnmips.

llvm-svn: 204337
 2014-03-20 11:51:58 +00:00
Zoran Jovanovic 87d13e5ec1 Implementation of microMIPS 16-bit instructions MOVE and JALR. 
Differential Revision: http://llvm-reviews.chandlerc.com/D3112

llvm-svn: 204325
 2014-03-20 10:18:24 +00:00
Zoran Jovanovic 8876be39c7 Support for microMIPS FPU instructions 2. 
llvm-svn: 198009
 2013-12-25 10:09:27 +00:00
Zoran Jovanovic ce02486d16 Support for microMIPS FPU instructions 1. 
llvm-svn: 197815
 2013-12-20 15:44:08 +00:00
Zoran Jovanovic 8e918c3c4d Support for microMIPS control instructions. 
llvm-svn: 197696
 2013-12-19 16:25:00 +00:00
Zoran Jovanovic ccb70caa13 Support for microMIPS trap instruction with immediate operands. 
llvm-svn: 194569
 2013-11-13 13:15:03 +00:00
Zoran Jovanovic c18b6d1083 Support for microMIPS trap instructions 1. 
llvm-svn: 194205
 2013-11-07 14:35:24 +00:00
Zoran Jovanovic 8a80aa76c8 Support for microMIPS branch instructions. 
llvm-svn: 193992
 2013-11-04 14:53:22 +00:00
Zoran Jovanovic 507e084a18 Support for microMIPS jump instructions 
llvm-svn: 193623
 2013-10-29 16:38:59 +00:00
Zoran Jovanovic fc26cfcde7 Fixed bug when generating Load Upper Immediate microMIPS instruction. 
llvm-svn: 190746
 2013-09-14 07:35:41 +00:00
Zoran Jovanovic ab85278137 Support for misc microMIPS instructions. 
llvm-svn: 190744
 2013-09-14 06:49:25 +00:00
Akira Hatanaka 2c544d8ed5 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is 
equivalent to "beq $zero, $zero, offset".

llvm-svn: 190220
 2013-09-06 23:40:15 +00:00
Vladimir Medic 457ba56b05 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
llvm-svn: 190152
 2013-09-06 12:53:21 +00:00
Vladimir Medic e0fbb44a48 This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
llvm-svn: 190148
 2013-09-06 12:41:17 +00:00
Vladimir Medic 8277c1874a This patch implements trap instructions for mips. The test cases are added. 
llvm-svn: 189213
 2013-08-26 10:02:40 +00:00
Vladimir Medic 939877ee14 This patch implements ei and di instructions for mips. Test cases are added. 
llvm-svn: 188176
 2013-08-12 13:07:23 +00:00
Vladimir Medic d3dade29f5 Moving definition of MnemonicContainsDot field from class Instruction to class AsmParser as suggested. 
llvm-svn: 187569
 2013-08-01 09:25:27 +00:00
Akira Hatanaka 8f69d7f0c0 [mips] Delete instruction format for "bal". 
llvm-svn: 187443
 2013-07-30 20:42:19 +00:00
Akira Hatanaka 8bce21c154 [mips] Fix FP conditional move instructions to have explicit FP condition code 
register operands.

llvm-svn: 187242
 2013-07-26 20:51:20 +00:00
Akira Hatanaka 1fb1b8b811 [mips] Fix FP branch instructions to have explicit FP condition code register 
operands.

llvm-svn: 187238
 2013-07-26 20:13:47 +00:00
Vladimir Medic 29410f9c91 Implement eret and deret(return from exception) instructions for Mips. Test examples are given. 
llvm-svn: 186507
 2013-07-17 14:05:19 +00:00
Vladimir Medic 64828a1f73 This patch represents Mips utilization of r186388 code that alows asm matcher to emit mnemonics contain '.' characters. This makes asm parser code simpler and more efficient. 
llvm-svn: 186397
 2013-07-16 10:07:14 +00:00
Vladimir Medic bcf1ca08e0 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 186151
 2013-07-12 09:25:35 +00:00
Vladimir Medic 524ad0e46e Reverting commit r185999 due to buildboot failure. 
llvm-svn: 186000
 2013-07-10 12:26:26 +00:00
Vladimir Medic e84de1e101 Add support for Mips break and syscall insructions. The corresponding test cases are added. 
llvm-svn: 185999
 2013-07-10 10:18:10 +00:00
Akira Hatanaka 1cb024207f [mips] Trap on integer division by zero. 
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
 2013-05-20 18:07:43 +00:00
Akira Hatanaka f0aa6c9101 [mips] Add definitions of micromips load and store instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180241
 2013-04-25 01:21:25 +00:00
Akira Hatanaka cd9b74a599 [mips] Add definitions of micromips shift instructions. 
Patch by Zoran Jovanovic.

llvm-svn: 180238
 2013-04-25 01:11:15 +00:00
Akira Hatanaka be6a818fd4 [mips] First patch which adds support for micromips. 
This patch adds support for recoded (meaning assembly-language compatible to
standard mips32) arithmetic 32-bit instructions.

Patch by Zoran Jovanovic.

llvm-svn: 179873
 2013-04-19 19:03:11 +00:00
Akira Hatanaka 061d1ea5da [mips] Add definition of JALR instruction which has two register operands. Change the 
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
 2013-02-07 19:48:00 +00:00
Akira Hatanaka 556135d813 [mips] Make NOP a pseudo instruction and expand it to "sll $zero, $zero, 0". 
llvm-svn: 174546
 2013-02-06 21:50:15 +00:00
Akira Hatanaka e067e5a13f [mips] 80 columns. 
llvm-svn: 171515
 2013-01-04 19:38:05 +00:00
Akira Hatanaka e36e2f6876 [mips] Refactor instructions which move data from or to coprocessors. 
llvm-svn: 171510
 2013-01-04 19:13:49 +00:00
Akira Hatanaka 6ac2fc4976 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.

llvm-svn: 170956
 2012-12-21 23:21:32 +00:00
Akira Hatanaka beea8a34c3 [mips] Refactor SYNC and multiply/divide instructions. 
llvm-svn: 170955
 2012-12-21 23:17:36 +00:00
Akira Hatanaka 31ddec5887 [mips] Refactor BAL instructions. 
llvm-svn: 170954
 2012-12-21 23:15:59 +00:00
Akira Hatanaka a158042a56 [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
llvm-svn: 170952
 2012-12-21 23:03:50 +00:00
Akira Hatanaka e738efc95b [mips] Refactor LUI instruction. 
llvm-svn: 170944
 2012-12-21 22:46:07 +00:00
Akira Hatanaka 895e1cb2aa [mips] Refactor count leading zero or one instructions. 
llvm-svn: 170942
 2012-12-21 22:43:58 +00:00
Akira Hatanaka 4f4c4aa05e [mips] Refactor sign-extension-in-register instructions. 
llvm-svn: 170940
 2012-12-21 22:41:52 +00:00
Akira Hatanaka b14c6e4e5f [mips] Refactor instructions which copy from and to HI/LO registers. 
llvm-svn: 170939
 2012-12-21 22:39:17 +00:00
Akira Hatanaka e7f1acc7c0 [mips] Refactor SLT (set on less than) instructions. Separate encoding 
information from the rest. 

llvm-svn: 170664
 2012-12-20 04:27:52 +00:00
Akira Hatanaka bbd197e9c4 [mips] Refactor unconditional branch instruction. Separate encoding information 
from the rest. 

llvm-svn: 170663
 2012-12-20 04:22:39 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.

llvm-svn: 170659
 2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.

llvm-svn: 170657
 2012-12-20 04:10:13 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.

llvm-svn: 170650
 2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.

llvm-svn: 170649
 2012-12-20 03:44:41 +00:00