7149cfcda3
Fix a mistake in my previous change r105437: don't access operand 2 and assume
...
that it is an immediate before checking that the instruction is an
EXTRACT_SUBREG.
llvm-svn: 105585
2010-06-07 23:48:46 +00:00
7398758719
Add some basic debug output.
...
llvm-svn: 105561
2010-06-07 22:32:10 +00:00
723d242a95
Handle dbg_value instructions (i.e., skip them) when generating IT blocks.
...
rdar://7797940
llvm-svn: 105557
2010-06-07 21:48:47 +00:00
6201b991a2
Cleanup. Process the dbg_values separately
...
llvm-svn: 105554
2010-06-07 21:28:55 +00:00
fb8ed43349
Make bugpoint dead-argument-hacking actually work, and actually test it.
...
llvm-svn: 105551
2010-06-07 20:20:33 +00:00
ebf2e977cf
The FoldingSet hash data includes pointer values, so it isn't
...
determinstic. Instead, give SCEV objects an arbitrary sequence
number.
llvm-svn: 105548
2010-06-07 19:36:14 +00:00
3553feed79
Optimize this code somewhat by taking advantage of the fact
...
that the operands are sorted.
llvm-svn: 105546
2010-06-07 19:20:57 +00:00
cfcd0e12cf
Another place where the code wanted to access the argument list and not all of
...
the operands.
llvm-svn: 105545
2010-06-07 19:18:58 +00:00
a2effb6452
Micro-optimize this, to speed up this hotspot in debug builds a little.
...
llvm-svn: 105544
2010-06-07 19:16:37 +00:00
18a4b46404
Micro-optimize this.
...
llvm-svn: 105542
2010-06-07 19:12:54 +00:00
0f445f328e
Move exit check where it really belongs.
...
llvm-svn: 105541
2010-06-07 19:12:21 +00:00
70910a6ab6
Optimize ScalarEvolution's SCEVComplexityCompare predicate: don't go
...
scrounging through SCEVUnknown contents and SCEVNAryExpr operands;
instead just do a simple deterministic comparison of the precomputed
hash data.
Also, since this is more precise, it eliminates the need for the slow
N^2 duplicate detection code.
llvm-svn: 105540
2010-06-07 19:06:13 +00:00
a3bba3371a
Create new accessors to get arguments for call/invoke instructions. It breaks
...
encapsulation to force the users of these classes to know about the internal
data structure of the Operands structure. It also can lead to errors, like in
the MSIL writer.
llvm-svn: 105539
2010-06-07 19:05:06 +00:00
1850444000
Partial specialization was not checking the callsite to make sure it was using the same constants as the specialization, leading to calls to the wrong specialization. Patch by Takumi Nakamura\!
...
llvm-svn: 105528
2010-06-05 14:50:21 +00:00
e4f45cc88f
This bug is also present in MSVC10. Requested by Elrood on IRC.
...
llvm-svn: 105527
2010-06-05 12:40:43 +00:00
fdd2614330
revert r105521, which is breaking the buildbots with stuff like this:
...
In file included from X86InstrInfo.cpp:16:
X86GenInstrInfo.inc:2789: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2790: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2792: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2793: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2808: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2809: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2816: error: integer constant is too large for 'long' type
X86GenInstrInfo.inc:2817: error: integer constant is too large for 'long' type
llvm-svn: 105524
2010-06-05 04:17:30 +00:00
594fa26317
Initial AVX support for some instructions. No patterns matched
...
yet, only assembly encoding support.
llvm-svn: 105521
2010-06-05 03:53:24 +00:00
81ef35b3ca
Improvements to tail call code. No functional effect
...
unless using -arm-tail-calls.
llvm-svn: 105515
2010-06-05 00:51:39 +00:00
520913cf9e
getFoldedOffsetOf no longer does anything special with vector types.
...
llvm-svn: 105514
2010-06-05 00:47:34 +00:00
3ca391027f
Revert 105492 & 105493 due to a testcase regression. Radar 7424645.
...
llvm-svn: 105511
2010-06-05 00:39:29 +00:00
bbfb6aca92
LSR needs to remember inserted instructions even in postinc mode, because
...
there could be multiple subexpressions within a single expansion which
require insert point adjustment. This fixes PR7306.
llvm-svn: 105510
2010-06-05 00:33:07 +00:00
df1a7f83bf
Fix some liveout handling related to tail calls, see comments.
...
I don't think this ever resulted in problems on x86, but it
would on ARM.
llvm-svn: 105509
2010-06-05 00:30:45 +00:00
a03e6f85fe
Re-apply 105308 with fix.
...
llvm-svn: 105502
2010-06-04 23:28:13 +00:00
67b4403101
Don't track users of undef values; they aren't interesting for
...
register pressure.
llvm-svn: 105501
2010-06-04 23:16:05 +00:00
a1e08fb256
Make if-conversion ignore dbg_value instructions in its analysis. rdar://7797940
...
llvm-svn: 105498
2010-06-04 23:01:26 +00:00
7c015988fe
Support for nested functions/classes in debug output. Radar 7424645.
...
llvm-svn: 105492
2010-06-04 22:36:03 +00:00
36da24b546
Copy location info for current function argument from dbg.declare if respective store instruction does not have any location info.
...
llvm-svn: 105490
2010-06-04 22:27:30 +00:00
50d229e6b3
Skip dbg_value instructions when scanning instructions in register scavenging.
...
llvm-svn: 105481
2010-06-04 20:18:30 +00:00
538b413ccb
Fix normalization and de-normalization of non-affine SCEVs.
...
llvm-svn: 105480
2010-06-04 19:16:34 +00:00
864827afb0
Keep track of the call instructions whose clobber lists were skipped during fast
...
register allocation.
Process all of the clobber lists at the end of the function, marking the
registers as used in MachineRegisterInfo.
This is necessary in case the calls clobber callee-saved registers (sic).
llvm-svn: 105473
2010-06-04 18:08:29 +00:00
d1b9311afa
More thoroughly disable tails calls by default.
...
8060143, although this doesn't fix the real problem with tail call.
llvm-svn: 105472
2010-06-04 18:04:24 +00:00
3548803f62
Another fix to prevent debug info from affecting codegen. rdar://7797940
...
llvm-svn: 105470
2010-06-04 17:57:34 +00:00
4e5e6a8973
more dbg_value adjustments so debug info doesn't affect codegen
...
llvm-svn: 105454
2010-06-04 01:23:30 +00:00
622cdd2297
Fixed a bug during widening where we would avoid legalizing a node. When we
...
replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE
when recursively updating nodes. Since OpA has been processed, the new uses are
not examined again. The patch checks if this occurred and it it did, updates the
new uses of OpA to use OpB.
llvm-svn: 105453
2010-06-04 01:20:10 +00:00
1bcdf32d22
fix typo
...
llvm-svn: 105441
2010-06-04 00:15:00 +00:00
d8a9a04739
For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and
...
VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR
node corresponds closely to REG_SEQUENCE but I couldn't use it here because
its operands do not get legalized. That is pretty awful, but I guess it
makes sense for other targets. Instead, I have added an ARM-specific version
of BUILD_VECTOR that will have its operands properly legalized.
This fixes the rest of Radar 7872877.
llvm-svn: 105439
2010-06-04 00:04:02 +00:00
a733daf18c
Add some missing checks in TwoAddressInstructionPass::CoalesceExtSubRegs.
...
Check that all the instructions are in the same basic block, that the
EXTRACT_SUBREGs write to the same subregs that are being extracted, and that
the source and destination registers are in the same regclass. Some of
these constraints can be relaxed with a bit more work. Jakob suggested
that the loop that checks for subregs when NewSubIdx != 0 should use the
"nodbg" iterator, so I made that change here, too.
llvm-svn: 105437
2010-06-03 23:53:58 +00:00
01edd68225
Cleanup 80-column and trim trailing whitespace
...
llvm-svn: 105435
2010-06-03 23:49:57 +00:00
b30b81edb6
Teach the ARM load-store optimizer to deal with dbg_value instructions.
...
llvm-svn: 105427
2010-06-03 22:41:15 +00:00
d679ff7330
Early implementation of tail call for ARM.
...
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.
llvm-svn: 105413
2010-06-03 21:09:53 +00:00
d83e3e7750
Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It
...
needs to demand the high bits because it's asserting that they're zero.
llvm-svn: 105406
2010-06-03 20:21:33 +00:00
30093b5d8b
Revert 105308.
...
llvm-svn: 105399
2010-06-03 18:28:31 +00:00
f82aea634c
Machine sink could potentially sink instructions into a block where the physical
...
registers it defines then interfere with an existing preg live range.
For instance, if we had something like these machine instructions:
BB#0
... = imul ... EFLAGS<imp-def,dead>
test ..., EFLAGS<imp-def>
jcc BB#2 EFLAGS<imp-use>
BB#1
... ; fallthrough to BB#2
BB#2
... ; No code that defines EFLAGS
jcc ... EFLAGS<imp-use>
Machine sink will come along, see that imul implicitly defines EFLAGS, but
because it's "dead", it assumes that it can move imul into BB#2. But when it
does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and
messes up the condition code for the jump (and pretty much anything else which
relies upon it being correct).
The solution is to know which pregs are live going into a basic block. However,
that information isn't calculated at this point. Nor does the LiveVariables pass
take into account non-allocatable physical registers. In lieu of this, we do a
*very* conservative pass through the basic block to determine if a preg is live
coming out of it.
llvm-svn: 105387
2010-06-03 07:54:20 +00:00
b0e1a458ce
Add first pass at darwin tls compiler support.
...
llvm-svn: 105381
2010-06-03 04:07:48 +00:00
f67fe3b1e8
One underscore, not two.
...
llvm-svn: 105379
2010-06-03 04:02:59 +00:00
dbbbf73c96
Implement expansion in type legalization for add/sub with overflow. The
...
expansion is the same as that used by LegalizeDAG.
The resulting code sucks in terms of performance/codesize on x86-32 for a
64-bit operation; I haven't looked into whether different expansions might be
better in general.
llvm-svn: 105378
2010-06-03 03:49:50 +00:00
ceb13f2af3
Remove some already-fixed README entries.
...
llvm-svn: 105377
2010-06-03 01:47:31 +00:00
a59b7a72b9
Remove README entry which no longer compiles to something sane.
...
llvm-svn: 105376
2010-06-03 01:16:51 +00:00
1f41303260
Remove a fixed item, update a couple partially-fixed items.
...
llvm-svn: 105375
2010-06-03 01:01:48 +00:00
4029596f93
Use the fast register allocator by default for -O0 builds.
...
This affects both llvm-gcc and clang.
llvm-svn: 105372
2010-06-03 00:39:06 +00:00
818e4df2b4
Use readsWritesVirtualRegister instead of counting uses and defs when inserting
...
spills and reloads.
This means that a partial define of a register causes a reload so the other
parts of the register are preserved.
The reload can be prevented by adding an <imp-def> operand for the full
register. This is already done by the coalescer and live interval analysis where
relevant.
llvm-svn: 105369
2010-06-03 00:07:47 +00:00
42c642cd24
Add full register <imp-def> operands when the coalescer is creating partial
...
register updates.
These operands tell the spiller that the other parts of the partially defined
register are don't-care, and a reload is not necessary.
llvm-svn: 105361
2010-06-02 23:22:11 +00:00
df84e8baf7
Speedup bitcode writer. Do not walk all values for all functions to emit function local metadata. In one testcase, probably worst case scenario, the 70x speed up is seen.
...
llvm-svn: 105360
2010-06-02 23:05:04 +00:00
7ee730eb40
Compulsive reformating. No functionalitical changes.
...
llvm-svn: 105359
2010-06-02 23:04:26 +00:00
a8ad97743d
Slightly change the meaning of the reMaterialize target hook when the original
...
instruction defines subregisters.
Any existing subreg indices on the original instruction are preserved or
composed with the new subreg index.
Also substitute multiple operands mentioning the original register by using the
new MachineInstr::substituteRegister() function. This is necessary because there
will soon be <imp-def> operands added to non read-modify-write partial
definitions. This instruction:
%reg1234:foo = FLAP %reg1234<imp-def>
will reMaterialize(%reg3333, bar) like this:
%reg3333:bar-foo = FLAP %reg333:bar<imp-def>
Finally, replace the TargetRegisterInfo pointer argument with a reference to
indicate that it cannot be NULL.
llvm-svn: 105358
2010-06-02 22:47:25 +00:00
84511e1526
Clean up 80 column violations. No functional change.
...
llvm-svn: 105350
2010-06-02 21:53:11 +00:00
f2dffcef82
Remove the TargetRegisterClass member from CalleeSavedInfo
...
llvm-svn: 105344
2010-06-02 20:02:30 +00:00
6e3d5af945
Fix comment so it doesn't include comments which are irrelevant to the x86
...
backend. Add a FIXME noting what can be fixed here.
llvm-svn: 105342
2010-06-02 19:35:46 +00:00
a690618c58
Use comments to document non-obvious code rather than
...
mailing list archives.
llvm-svn: 105341
2010-06-02 19:13:40 +00:00
c2254f6b98
Skip identical instruction while calculating DBG_VALUE range.
...
llvm-svn: 105340
2010-06-02 19:05:13 +00:00
2d35a9e810
Rename canCombinedSubRegIndex method to something more grammatically correct
...
and tidy up the comment describing it.
llvm-svn: 105339
2010-06-02 18:54:47 +00:00
94801a47f8
Replace ARM's getCalleeSavedRegClasses with a simpler solution
...
llvm-svn: 105335
2010-06-02 17:54:50 +00:00
21ccf05b4c
Use local small vector.
...
llvm-svn: 105332
2010-06-02 16:42:51 +00:00
7881a64a50
Remove unused function.
...
llvm-svn: 105325
2010-06-02 15:44:20 +00:00
848548300d
Not all entries in the range will have an SUnit. Check for that when looking
...
for debug information.
llvm-svn: 105324
2010-06-02 15:29:36 +00:00
ef2b6ce00a
cleanup
...
llvm-svn: 105322
2010-06-02 13:53:17 +00:00
c08ecba597
Remove uses of getCalleeSavedRegClasses from outside the
...
backends and removes the virtual declaration. With that out of the way
I should be able to cleanup one backend at a time.
llvm-svn: 105321
2010-06-02 12:39:06 +00:00
a2da22734f
Enable machine cse of instructions which define physical registers.
...
llvm-svn: 105308
2010-06-02 01:08:27 +00:00
526e6d045f
Don't try to custom-lower 64-bit add-with-overflow and friends on x86-32; the
...
x86 backend currently doesn't know how to handle them.
This doesn't really fix anything because LegalizeTypes doesn't know how to
handle them either. We do get a better error message, though.
llvm-svn: 105305
2010-06-02 00:27:18 +00:00
f4a34b97b8
Fix an obvious mistake: don't change the operands until all of them have been
...
checked and it is safe to proceed with the changes.
llvm-svn: 105304
2010-06-02 00:16:08 +00:00
6382c9c681
Remove outdated README entries.
...
llvm-svn: 105303
2010-06-02 00:10:36 +00:00
12ac8f0352
Update debug information when breaking anti-dependencies. rdar://7759363
...
llvm-svn: 105300
2010-06-01 23:48:44 +00:00
7b0ac865a4
Properly compose subregister indices when coalescing.
...
The comment about ordering of subreg indices is no longer true.
This exposed a bug in the new substVirtReg method that is also fixed.
llvm-svn: 105294
2010-06-01 22:39:25 +00:00
5ba76b94f8
Remove unused code
...
llvm-svn: 105293
2010-06-01 21:56:30 +00:00
d43e0ca916
Ignore line number of debug value in undefined register.
...
llvm-svn: 105292
2010-06-01 21:43:09 +00:00
0e20dc5cd6
fix think-o
...
llvm-svn: 105291
2010-06-01 21:35:50 +00:00
47a0724425
Fix the allocation of shadow space for the Win64 calling convention
...
in X86FastISel. Patch by Jan Sjodin.
llvm-svn: 105290
2010-06-01 21:09:47 +00:00
b69c68742a
Simplify things a bit more. Fix prototype to use SmallVectorImpl and
...
change a few SmallVectors to vanilla C arrays.
llvm-svn: 105289
2010-06-01 21:06:46 +00:00
49a372cebc
Fix the noalias checking so that it doesn't worry about
...
an argument aliasing itself. Thanks Duncan!
llvm-svn: 105288
2010-06-01 20:51:40 +00:00
b0c76394a3
Keep track of incoming debug value of unused argument.
...
Radar 7927666.
llvm-svn: 105285
2010-06-01 19:59:01 +00:00
b782caa393
Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.
...
llvm-svn: 105283
2010-06-01 18:35:14 +00:00
b24d5c6ce2
Add a FIXME
...
llvm-svn: 105282
2010-06-01 18:06:35 +00:00
a37af16221
mirror of r105280 changes for LowerInvoke, which uses the same basic logic here
...
llvm-svn: 105281
2010-06-01 18:04:56 +00:00
74d8345512
When processing function arguments when splitting live ranges across invokes,
...
handle structs passed by value via an extract/insert pair, as a bitcast
won't work on a struct. rdar://7742824
llvm-svn: 105280
2010-06-01 18:04:09 +00:00
7352167560
Use SmallVector instead of std::vector.
...
llvm-svn: 105279
2010-06-01 17:56:41 +00:00
d44677ba69
Refactor some SSE 2 unpack instructions
...
llvm-svn: 105276
2010-06-01 17:02:50 +00:00
a76715fc88
Don't call flush() at a library level which isn't checking for errors
...
and doesn't know where the output is going.
llvm-svn: 105274
2010-06-01 16:31:34 +00:00
8916358f97
Fix handling of 'load' nodes.
...
llvm-svn: 105269
2010-06-01 13:34:47 +00:00
4c904fa797
Fix PR7272: when inlining through a callsite with byval arguments,
...
the newly created allocas may be used by inlined calls, so these
need to have their tail call flags cleared. Fixes PR7272.
llvm-svn: 105255
2010-05-31 21:00:26 +00:00
14c46517b5
fix PR6623: when optimizing for size, don't inline memcpy/memsets
...
that are too large. This causes the freebsd bootloader to be too
large apparently.
It's unclear if this should be an -Os or -Oz thing. Thoughts welcome.
llvm-svn: 105228
2010-05-31 17:30:14 +00:00
b4a773b452
the 'limit' argument to FindOptimalMemOpLowering is unsigned, not uint64_t.
...
llvm-svn: 105226
2010-05-31 17:12:23 +00:00
5ac57e3440
Avoid swap when a copy suffices.
...
llvm-svn: 105220
2010-05-31 12:50:41 +00:00
aee2632be3
The memcpy intrinsic only takes i8* for %src and %dst, so cast them to that
...
first. Fixes PR7265.
llvm-svn: 105206
2010-05-31 06:16:35 +00:00
a97311f152
Use `llvm::next' instead of `next' to make VC++ 2010 happy.
...
llvm-svn: 105168
2010-05-30 13:14:21 +00:00
a09d95412e
Some A9 load/store cleanups
...
llvm-svn: 105109
2010-05-29 19:25:39 +00:00
2a21aef8f2
Some rough approximations for load/stores on A9
...
llvm-svn: 105108
2010-05-29 19:25:34 +00:00
d4c7cceb70
NEON/VFP stuff can be issued only via Pipe1 on A9
...
llvm-svn: 105107
2010-05-29 19:25:29 +00:00
94d7fd88fd
Add some integer instruction itineraries for A9
...
llvm-svn: 105106
2010-05-29 19:25:17 +00:00
4db93c9700
Reorder some code in SelectionDAGBuilder.
...
llvm-svn: 105105
2010-05-29 17:53:24 +00:00
d16aa541af
SelectionDAG shouldn't have a FunctionLoweringInfo member. RegsForValue
...
shouldn't have a TargetLoweringInfo member. And FunctionLoweringInfo::set
doesn't needs its EnableFastISel argument.
llvm-svn: 105101
2010-05-29 17:03:36 +00:00
c488e92f0b
Remove unused function.
...
llvm-svn: 105100
2010-05-29 14:03:51 +00:00
707b7cc429
Remove schedule-livein-copies. It's not being used.
...
llvm-svn: 105095
2010-05-29 02:23:39 +00:00
27c4933e02
Fix PR7193: if sibling call address can take a register, make sure there are enough registers available by counting inreg arguments.
...
llvm-svn: 105092
2010-05-29 01:35:22 +00:00
ab6223949e
Handle composed subreg indices when processing REQ_SEQUENCE instructions.
...
llvm-svn: 105066
2010-05-29 00:14:14 +00:00
032f3261a2
Doh. Machine LICM is re-initializing the CSE map over and over. Patch by Anna Zaks. rdar://8037934.
...
llvm-svn: 105065
2010-05-29 00:06:36 +00:00
e02996ca8f
Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
...
were overspecified when inheriting sub-subregisters, for instance:
R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.
This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.
llvm-svn: 105063
2010-05-28 23:48:29 +00:00
cc2efe11db
Fix some latency computation bugs: if the use is not a machine opcode do not just return zero.
...
llvm-svn: 105061
2010-05-28 23:26:21 +00:00
bf91499f1a
Schedule high latency instructions for latency reduction even if they are not vfp / NEON instructions.
...
llvm-svn: 105060
2010-05-28 23:25:23 +00:00
e8be73f3e7
Fix comment typos.
...
llvm-svn: 105059
2010-05-28 23:24:28 +00:00
1f79289806
More SSE 1 & 2 merge, this time with logical instructions
...
llvm-svn: 105014
2010-05-28 22:47:03 +00:00
34709d06c0
Fix AliasDebugger to be aware of operand values too.
...
llvm-svn: 105012
2010-05-28 22:31:51 +00:00
0fa67e479a
Add lint checks for function attributes.
...
llvm-svn: 105009
2010-05-28 21:43:57 +00:00
0d7f3b8195
Split the logic behind CastInst::isNoopCast into a separate static function,
...
as is done with most other cast opcode predicates.
llvm-svn: 105008
2010-05-28 21:41:37 +00:00
4c71e08ed8
MC/X86: Add alias for movzx.
...
llvm-svn: 105005
2010-05-28 21:20:21 +00:00
b29228905f
MC/X86: Add alias for fwait.
...
llvm-svn: 105001
2010-05-28 20:59:10 +00:00
76413597a9
Fix the use of x86 control and debug registers so that the assertion failure in
...
getX86RegNum() does not happen. Patch by Shantonu Sen!
llvm-svn: 104994
2010-05-28 19:01:27 +00:00
64824ea99f
Add a TargetRegisterInfo::composeSubRegIndices hook with a default
...
implementation that is correct for most targets. Tablegen will override where
needed.
Add MachineOperand::subst{Virt,Phys}Reg methods that correctly handle existing
subreg indices when sustituting registers.
llvm-svn: 104985
2010-05-28 18:18:53 +00:00
b342e09b5e
correct retattr
...
llvm-svn: 104980
2010-05-28 18:03:48 +00:00
0b20fdaff0
Cosmetic cleanup. No functional change.
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llvm-svn: 104974
2010-05-28 17:51:20 +00:00
c575ec61ea
Fix lint's memcpy and memmove checks, and its basic block traversal.
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llvm-svn: 104970
2010-05-28 17:44:00 +00:00
37eb2c24b9
make sure accesses to set up the jmpbuf don't get moved after it by the scheduler. Add a missing \n.
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llvm-svn: 104967
2010-05-28 17:37:40 +00:00
fb85820f9a
Minor code simplification.
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llvm-svn: 104959
2010-05-28 16:50:23 +00:00
feaeb36edf
Fix a redundant-return warning.
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llvm-svn: 104958
2010-05-28 16:50:01 +00:00
862f034188
Detect self-referential values.
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llvm-svn: 104957
2010-05-28 16:45:33 +00:00
c1e216583f
Revert 104841, 104842, 104876 due to buildbot failures. Radar 7424645.
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llvm-svn: 104953
2010-05-28 16:41:07 +00:00
cef9fc37f4
Eli pointed out that va_arg instruction result values don't
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reference the stack.
llvm-svn: 104951
2010-05-28 16:34:49 +00:00
54d7aaa819
Teach lint how to look through simple store+load pairs and other
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effective no-op constructs, to make it more effective on
unoptimized IR.
llvm-svn: 104950
2010-05-28 16:21:24 +00:00
826bdf8c10
Move FindAvailableLoadedValue isSafeToLoadUnconditionally out of
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lib/Transforms/Utils and into lib/Analysis so that Analysis passes
can use them.
llvm-svn: 104949
2010-05-28 16:19:17 +00:00
a3b6c4b529
ConstantFoldConstantExpression can theoretically return null.
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llvm-svn: 104948
2010-05-28 16:12:08 +00:00
df5d7dcef1
Teach instcombine to promote alloca array sizes.
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llvm-svn: 104945
2010-05-28 15:09:00 +00:00
ddba4b725a
Add a lint check for returning the address of stack memory.
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llvm-svn: 104936
2010-05-28 04:33:42 +00:00
05a6555acb
Fix instcombine's handling of alloca to accept non-i32 types.
...
llvm-svn: 104935
2010-05-28 04:33:04 +00:00
9da5bb0756
Bitcode support for allocas with arbitrary array size types.
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llvm-svn: 104915
2010-05-28 01:38:28 +00:00
3e0fbafab2
Fix typo.
...
llvm-svn: 104914
2010-05-28 01:29:50 +00:00
e2099e8088
Fix typo.
...
llvm-svn: 104913
2010-05-28 01:17:51 +00:00
2140a74979
Eliminate the restriction that the array size in an alloca must be i32.
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This will help reduce the amount of casting required on 64-bit targets.
llvm-svn: 104911
2010-05-28 01:14:11 +00:00
b6112e8706
Add the cc_out operand for t2RSBrs instructions. I missed this when I changed
...
the instruction class for t2RSB to add that operand in svn r104582.
Radar 8033757.
llvm-svn: 104907
2010-05-28 00:27:15 +00:00
b613ae2c89
Add a -regalloc=default option that chooses a register allocator based on the -O
...
optimization level.
This only really affects llc for now because both the llvm-gcc and clang front
ends override the default register allocator. I intend to remove that code later.
llvm-svn: 104904
2010-05-27 23:57:25 +00:00
faa3abbe39
Update the saved stack pointer in the sjlj function context following either
...
an alloca() or an llvm.stackrestore(). rdar://8031573
llvm-svn: 104900
2010-05-27 23:49:24 +00:00
c2ebe0334a
Use report_fatal_error, not llvm_unreachable.
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llvm-svn: 104899
2010-05-27 23:45:31 +00:00
c9f532dddc
back out 104862/104869. Can reuse stacksave after all. Very cool.
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llvm-svn: 104897
2010-05-27 23:11:57 +00:00
288999b829
Factor out the handler work from SignalHandler into a helper function,
...
and change llvm::sys::RunInterruptHandlers to call that function directly
instead of calling SignalHandler, because the rest of SignalHandler
invokes side effects which aren't appropriate, including raising the
signal.
llvm-svn: 104896
2010-05-27 23:11:55 +00:00
3d3ee87d4e
llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.
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llvm-svn: 104891
2010-05-27 22:08:38 +00:00
9738f64bd9
MC/X86: Add aliases for Jcc variants.
...
llvm-svn: 104890
2010-05-27 21:33:19 +00:00
6debf89587
Eliminate some unnessary Path::exists() calls.
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llvm-svn: 104888
2010-05-27 20:51:54 +00:00
a880546c65
Don't flush the raw_ostream in llvm::WriteBitcodeToFile; it's at
...
the wrong level. Clients which need to leave the stream open but
which still require the bitcode bits to be on disk should call
flush themselves.
llvm-svn: 104885
2010-05-27 20:26:51 +00:00
7a9dedf0ab
Do not drop location info for inlined function args.
...
llvm-svn: 104884
2010-05-27 20:25:04 +00:00
40e62dfdc0
Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' cases
...
should fall through to the 'H' case, but instead 'Q' was falling through to 'R'
so that it would do the wrong thing for a big-endian ARM target.
llvm-svn: 104883
2010-05-27 20:23:42 +00:00
9e43c07bc5
Mark some math lib intrinsic nodes Legal on SSE4.1.
...
No functional effect as these nodes are not generated yet.
llvm-svn: 104879
2010-05-27 20:12:41 +00:00
d9225cee20
Don't special-case stdout in llvm::WriteBitcodeToFile; just consider
...
it to be the caller's responsibility to provide a stream in binary
mode. This fixes a layering violation and avoids an outs() call.
llvm-svn: 104878
2010-05-27 20:06:51 +00:00
Bob Wilson