Commit Graph

375603 Commits

Author SHA1 Message Date
Simon Moll acaa6e4260 [NFC] Uniquify 'const' in TargetTransformInfoImpl.h
Some member functions of class TargetTransformInfoImplBase in
TargetTransformInfoImpl.h are marked const while others are not. Yet all
of the should be marked const since they are just providing default TTI
values. This patch fixes the inconsistency.

Authored-by: Jinzheng Tu <b1f6c1c4@gmail.com>

Reviewed By: simoll

Differential revision: https://reviews.llvm.org/D93573
2020-12-23 14:21:41 +01:00
Simon Moll c3acda0798 [VE] Vector 'and' isel and tests
Reviewed By: kaz7

Differential Revision: https://reviews.llvm.org/D93709
2020-12-23 13:29:29 +01:00
Alex Zinenko 7ed9cfc7b1 [mlir] Remove static constructors from LLVMType
LLVMType contains numerous static constructors that were initially introduced
for API compatibility with LLVM. Most of these merely forward to arguments to
`SpecificType::get` (MLIR defines classes for all types, unlike LLVM IR), while
some introduce subtle semantics differences due to different modeling of MLIR
types (e.g., structs are not auto-renamed in case of conflicts). Furthermore,
these constructors don't match MLIR idioms and actively prevent us from making
the LLVM dialect type system more open. Remove them and use `SpecificType::get`
instead.

Depends On D93680

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93681
2020-12-23 13:12:47 +01:00
Nathan James eb9483b210
[format] Add overload to parseConfiguration that accept llvm::MemoryBufferRef
This overload should be used for better diagnostics when parsing configurations.
Now a failure to parse will list the filename (or <command-line>) instead of just `YAML`.

Reviewed By: MyDeveloperDay

Differential Revision: https://reviews.llvm.org/D93633
2020-12-23 12:08:29 +00:00
Adrian Kuegel 25a02c3d1a Revert "PR24076, PR33655, C++ CWG 1558: Consider the instantiation-dependence of"
This reverts commit d3bf0bb189.
This causes compilation in certain cases to fail.
Reproducer TBD.
2020-12-23 12:31:52 +01:00
Christian Sigg 19a0d0a40c [mlir] Rename ConvertToLLVMPattern::isSupportedMemRefType() to isConvertibleAndHasIdentityMaps().
Reviewed By: ftynse, herhut

Differential Revision: https://reviews.llvm.org/D93752
2020-12-23 12:23:29 +01:00
Alex Zinenko 32a884c9c5 [mlir] Add translation of omp.wsloop to LLVM IR
Introduce a translation of OpenMP workshare loop construct to LLVM IR. This is
a minimalist version to enable the pipeline and currently only supports static
loop schedule (default in the specification) on non-collapsed loops. Other
features will be added on per-need basis.

Reviewed By: kiranchandramohan

Differential Revision: https://reviews.llvm.org/D92055
2020-12-23 11:52:28 +01:00
Christian Sigg 8451d4872e [mlir] NFC: Remove ConvertToLLVMPattern::getDataPtr(). All call sites use getStridedElementPtr() now.
Reviewed By: ftynse

Differential Revision: https://reviews.llvm.org/D93751
2020-12-23 11:35:01 +01:00
Alex Zinenko 65ba0cd395 [mlir] Modernize std-to-llvm operation conversion doc
This was long overdue. Replace the outdated type syntax with the new syntax,
and update the description of how memref load/stores are handled to reflect the
latest changes in the implementation.

Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D93555
2020-12-23 11:19:58 +01:00
Sebastian Neubauer 221fdedc69 [AMDGPU][GlobalISel] Fold flat vgpr + constant addresses
Use getPtrBaseWithConstantOffset in selectFlatOffsetImpl to fold more
vgpr+constant addresses.

Differential Revision: https://reviews.llvm.org/D93692
2020-12-23 10:40:30 +01:00
ShihPo Hung 6301871d06 [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac instructions
This patch defines vfwmacc, vfwnmacc, vfwmsc, vfwnmsac intrinsics
and lower to V instructions.
We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93693
2020-12-23 00:42:04 -08:00
Georgii Rymar bdef1f87ab [llvm-readobj] - Dump the ELF file type better.
Currently llvm-readelf might print "OS Specific/Processor Specific/<unknown>"
hint when dumping the ELF file type. The patch teaches llvm-readobj to do the same.

This fixes https://bugs.llvm.org/show_bug.cgi?id=40868

I am removing `Object/elf-unknown-type.test` test because it is not in the right place,
it is outdated and very limited.
The `readobj/ELF/file-types.test` checks the functionality much better.

Differential revision: https://reviews.llvm.org/D93689
2020-12-23 11:13:19 +03:00
Zakk Chen 032600b9ae [RISCV] Define vmerge/vfmerge intrinsics.
Define vmerge/vfmerge intrinsics and lower to V instructions.

Include support for vector-vector vfmerge by vmerge.vvm.

We work with @rogfer01 from BSC to come out this patch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93674
2020-12-23 00:07:09 -08:00
Evandro Menezes 4d47944393 [RISCV] Define the vfmin, vfmax RVV intrinsics
Define the vfmin, vfmax IR intrinsics for the respective V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: Evandro Menezes <evandro.menezes@sifive.com>

Differential Revision: https://reviews.llvm.org/D93673
2020-12-23 00:27:38 -06:00
Arthur Eubanks 0219cf7dfa [NewPM] Fix objc-arc-apelim pass typo 2020-12-22 21:40:43 -08:00
Kazu Hirata 3c707d73f2 [NewGVN] Remove for_each_found (NFC)
The last use of the function was removed on Sep 30, 2017 in commit
9b926e90d3.
2020-12-22 20:13:27 -08:00
Thomas Lively efe7f5ede0 [WebAssembly][NFC] Refactor SIMD load/store tablegen defs
Introduce `Vec` records, each bundling all information related to a single SIMD
lane interpretation. This lets TableGen definitions take a single Vec parameter
from which they can extract information rather than taking multiple redundant
parameters. This commit refactors all of the SIMD load and store instruction
definitions to use the new `Vec`s. Subsequent commits will similarly refactor
additional instruction definitions.

Differential Revision: https://reviews.llvm.org/D93660
2020-12-22 20:06:12 -08:00
Kazu Hirata e6fde1ae7d [MemorySSA] Use is_contained (NFC) 2020-12-22 19:58:54 -08:00
Matt Arsenault 581d13f8ae GlobalISel: Return APInt from getConstantVRegVal
Returning int64_t was arbitrarily limiting for wide integer types, and
the functions should handle the full generality of the IR.

Also changes the full form which returns the originally defined
vreg. Add another wrapper for the common case of just immediately
converting to int64_t (arguably this would be useful for the full
return value case as well).

One possible issue with this change is some of the existing uses did
break without conversion to getConstantVRegSExtVal, and it's possible
some without adequate test coverage are now broken.
2020-12-22 22:23:58 -05:00
Nico Weber 77fb45e59e [lld/mac] Add --version flag
It's an extension to ld64, but all the other ports have it, and
someone asked for it in PR43721.

While here, change the COFF help text to match the other ports.

Differential Revision: https://reviews.llvm.org/D93491
2020-12-22 22:06:39 -05:00
Matt Arsenault 8bf9cdeaee AMDGPU: Use Register 2020-12-22 21:55:59 -05:00
Matt Arsenault bac54639c7 AMDGPU: Add spilled CSR SGPRs to entry block live ins 2020-12-22 21:55:59 -05:00
ShihPo Hung ad0a7ad950 [RISCV] Add intrinsics for vf[n]macc/vf[n]msac/vf[n]madd/vf[n]msub instructions
This patch defines vfmadd/vfnmacc, vfmsac/vfnmsac, vfmadd/vfnmadd,
and vfmsub/vfnmsub lower to V instructions.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93691
2020-12-22 18:34:00 -08:00
ShihPo Hung 4268783998 [RISCV] Add intrinsics for vwmacc[u|su|us] instructions
This patch defines vwmacc[u|su|us] intrinsics and lower to V instructions.

We work with @rogfer01 from BSC to come out this patch.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93675
2020-12-22 18:17:39 -08:00
ShihPo Hung c8874464b5 [RISCV] Add intrinsics for vslide1up/down, vfslide1up/down instruction
This patch adds intrinsics for vslide1up, vslide1down, vfslide1up, vfslide1down.

Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com>
Co-Authored-by: ShihPo Hung <shihpo.hung@sifive.com>

Differential Revision: https://reviews.llvm.org/D93608
2020-12-22 18:14:22 -08:00
Matt Arsenault 29ed846d67 AMDGPU: Fix assert when checking for implicit operand legality 2020-12-22 20:56:24 -05:00
Matt Arsenault 5bec082834 VirtRegMap: Use Register 2020-12-22 20:56:14 -05:00
Arthur O'Dwyer 22cf54a7fb Replace `T(x)` with `reinterpret_cast<T>(x)` everywhere it means reinterpret_cast. NFC.
Differential Revision: https://reviews.llvm.org/D76572
2020-12-22 19:54:29 -05:00
Peter Collingbourne faac1c02c8 scudo: Move the management of the UseMemoryTagging bit out of the Primary. NFCI.
The primary and secondary allocators will need to share this bit,
so move the management of the bit to the combined allocator and
make useMemoryTagging() a free function.

Differential Revision: https://reviews.llvm.org/D93730
2020-12-22 16:52:54 -08:00
Peter Collingbourne e6b3db6309 scudo: Replace the Cache argument on MapAllocator with a Config argument. NFCI.
This will allow the secondary allocator to access the
MaySupportMemoryTagging bool.

Differential Revision: https://reviews.llvm.org/D93729
2020-12-22 16:52:48 -08:00
Stanislav Mekhanoshin d15119a02d [AMDGPU][GlobalISel] GlobalISel for flat scratch
It does not seem to fold offsets but this is not specific
to the flat scratch as getPtrBaseWithConstantOffset() does
not return the split for these tests unlike its SDag
counterpart.

Differential Revision: https://reviews.llvm.org/D93670
2020-12-22 16:33:06 -08:00
Stanislav Mekhanoshin ca4bf58e4e [AMDGPU] Support unaligned flat scratch in TLI
Adjust SITargetLowering::allowsMisalignedMemoryAccessesImpl for
unaligned flat scratch support. Mostly needed for global isel.

Differential Revision: https://reviews.llvm.org/D93669
2020-12-22 16:12:31 -08:00
Peter Collingbourne 6dfe5801e0 scudo: Move the configuration for the primary allocator to Config. NFCI.
This will allow the primary and secondary allocators to share
the MaySupportMemoryTagging bool.

Differential Revision: https://reviews.llvm.org/D93728
2020-12-22 14:54:40 -08:00
Chris Lattner 75a3f326c3 [IR] Add an ImplicitLocOpBuilder helper class for building IR with the same loc.
One common situation is to create a lot of IR at a well known location,
e.g. when doing a big rewrite from one dialect to another where you're expanding
ops out into lots of other ops.

For these sorts of situations, it is annoying to pass the location into
every create call.  As we discused in a few threads on the forum, a way to help
with this is to produce a new sort of builder that holds a location and provides
it to each of the create<> calls automatically.

This patch implements an ImplicitLocOpBuilder class that does this.  We've had
good experience with this in the CIRCT project, and it makes sense to upstream to
MLIR.

I picked a random pass to adopt it to show the impact, but I don't think there is
any particular need to force adopt it in the codebase.

Differential Revision: https://reviews.llvm.org/D93717
2020-12-22 14:47:33 -08:00
Joseph Huber 1c19804ebf [OpenMP] Add OpenMP Documentation for Libomptarget environment variables
Add support to the OpenMP web pages for environment variables supported
by Libomptarget and their usage.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D93723
2020-12-22 17:41:27 -05:00
Alex Zinenko 8de43b926f [mlir] Remove instance methods from LLVMType
LLVMType contains multiple instance methods that were introduced initially for
compatibility with LLVM API. These methods boil down to `cast` followed by
type-specific call. Arguably, they are mostly used in an LLVM cast-follows-isa
anti-pattern. This doesn't connect nicely to the rest of the MLIR
infrastructure and actively prevents it from making the LLVM dialect type
system more open, e.g., reusing built-in types when appropriate. Remove such
instance methods and replaces their uses with apporpriate casts and methods on
derived classes. In some cases, the result may look slightly more verbose, but
most cases should actually use a stricter subtype of LLVMType anyway and avoid
the isa/cast.

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D93680
2020-12-22 23:34:54 +01:00
Thomas Lively a781a706b9 [WebAssembly][SIMD] Rename shuffle, swizzle, and load_splats
These instructions previously used prefixes like v8x16 to signify that they were
agnostic between float and int interpretations. We renamed these instructions to
remove this form of prefix in https://github.com/WebAssembly/simd/issues/297 and
https://github.com/WebAssembly/simd/issues/316 and this commit brings the names
in LLVM up to date.

Differential Revision: https://reviews.llvm.org/D93722
2020-12-22 14:29:06 -08:00
Sam McCall f7a26127f2 [clangd] Release notes for b8c37153d5 2020-12-22 22:58:45 +01:00
Christian Sigg df6cbd37f5 [mlir] Lower gpu.memcpy to GPU runtime calls.
Reviewed By: herhut

Differential Revision: https://reviews.llvm.org/D93204
2020-12-22 22:49:19 +01:00
Sam McCall 3dbe471a26 [clangd] Use atomics instead of locks to track periodic memory trimming
Instead of always locking/unlocking a contended mutex, we now do one atomic read
in the common case, and one read + one exchange if the timer has expried.

Also use this for memory profiling which has similar/compatible requirements.

Differential Revision: https://reviews.llvm.org/D93726
2020-12-22 22:32:22 +01:00
Sanjay Patel f6929c0195 [SLP] add reduction tests for maxnum/minnum intrinsics; NFC 2020-12-22 16:05:39 -05:00
Sanjay Patel 0d15d4b6f4 [SLP] use operand index abstraction for number of operands
I think this is NFC currently, but the bug would be exposed
when we allow binary intrinsics (maxnum, etc) as candidates
for reductions.

The code in matchAssociativeReduction() is using
OperationData::getNumberOfOperands() when comparing whether
the "EdgeToVisit" iterator is in-bounds, so this code must
use the same (potentially offset) operand value to set
the "EdgeToVisit".
2020-12-22 16:05:39 -05:00
Nico Weber 57ffbe020a glld/mac] Don't add names of unreferenced symbols to string table
Before this, a hello world program would contain many many unnecessary
entries in its string table.

No behavior change, just makes the string table in the output smaller
and more like ld64's.

Differential Revision: https://reviews.llvm.org/D93711
2020-12-22 15:52:33 -05:00
Stephen Kelly 7ec7788ac1 Try to fix build on Windows 2020-12-22 20:25:58 +00:00
Craig Topper 53deef9e0b [RISCV] Remove unneeded !eq comparing a single bit value to 0/1 in RISCVInstrInfoVPseudos.td. NFC
Instead we can either use the bit directly. If it was checking for
0 we need to swap the operands or use !not.
2020-12-22 11:57:16 -08:00
Johannes Doerfert 7b0f9dd79a [OpenMP][Docs] Fix Typo 2020-12-22 13:06:23 -06:00
Shilei Tian 1eb082c2ea [OpenMP][Docs] Fixed a typo in the doc that can mislead users to a CMake error
When setting `LLVM_ENABLE_RUNTIMES`, lower case word should be used;
otherwise, it can cause a CMake error that specific path is not found.

Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D93719
2020-12-22 14:05:58 -05:00
Johannes Doerfert 9cb748724e [OpenMP][Docs] Add FAQ entry about math and complex on GPUs
Reviewed By: tianshilei1992

Differential Revision: https://reviews.llvm.org/D93718
2020-12-22 13:05:04 -06:00
Arnold Schwaighofer 333108e8be Add a llvm.coro.end.async intrinsic
The llvm.coro.end.async intrinsic allows to specify a function that is
to be called as the last action before returning. This function will be
inlined after coroutine splitting.

This function can contain a 'musttail' call to allow for guaranteed tail
calling as the last action.

Differential Revision: https://reviews.llvm.org/D93568
2020-12-22 10:52:28 -08:00
Stanislav Mekhanoshin ae8f4b2178 [AMDGPU] Folding of FI operand with flat scratch
Differential Revision: https://reviews.llvm.org/D93501
2020-12-22 10:48:04 -08:00