Commit Graph

123992 Commits

Author SHA1 Message Date
Dan Gohman 2dfc3b8be5 [WebAssembly] Remove done items from the README.txt.
llvm-svn: 253640
2015-11-20 02:51:38 +00:00
Dan Gohman 7bafa0eaef [WebAssembly] Add asserts that the expression stack is used in stack order.
llvm-svn: 253638
2015-11-20 02:33:24 +00:00
Dan Gohman b0992dafb3 [WebAssemby] Enforce FIFO ordering for instructions using stackified registers.
llvm-svn: 253634
2015-11-20 02:19:12 +00:00
Peter Collingbourne c85f4ced4d ScalarEvolution: do not set nuw when creating exprs of form <expr> + <all-ones>.
The nuw constraint will not be satisfied unless <expr> == 0.

This bug has been around since r102234 (in 2010!), but was uncovered by
r251052, which introduced more aggressive optimization of nuw scev expressions.

Differential Revision: http://reviews.llvm.org/D14850

llvm-svn: 253627
2015-11-20 01:26:13 +00:00
Eric Christopher eb027124af Split the argument unscheduling loop in the WebAssembly register
coloring pass. Turn the logic into "look for an insert point and
then move things past the insert point".

No functional change intended.

llvm-svn: 253626
2015-11-20 00:34:54 +00:00
Tobias Edler von Koch 49c9a6e802 [LTO] Add options to llvm-lto to select output format and dump merged module
This introduces two new options:
- "llvm-lto -save-merged-module -o outfile" dumps the LTO Module to
  outfile.merged.bc prior to CodeGen and after LTO optimizations have been run.
- "llvm-lto -filetype=asm -o outfile" makes llvm-lto emit assembly instead of
  object code in outfile.

Both are intended for use in lit tests.

llvm-svn: 253624
2015-11-20 00:13:05 +00:00
Tobias Edler von Koch 4d45090659 [LTO] Add option to emit assembly from LTOCodeGenerator
This adds a new API, LTOCodeGenerator::setFileType, to choose the output file
format for LTO CodeGen. A corresponding change to use this new API from
llvm-lto and a test case is coming in a separate commit.

Differential Revision: http://reviews.llvm.org/D14554

llvm-svn: 253622
2015-11-19 23:59:24 +00:00
Eric Christopher 8c3dbcab1d Fix a [-Werror,-Wcovered-switch-default] warning by removing the
unnecessary default case.

llvm-svn: 253621
2015-11-19 23:45:42 +00:00
Reid Kleckner cc2f6c35a3 [WinEH] Disable most forms of demotion
Now that the register allocator knows about the barriers on funclet
entry and exit, testing has shown that this is unnecessary.

We still demote PHIs on unsplittable blocks due to the differences
between the IR CFG and the Machine CFG.

llvm-svn: 253619
2015-11-19 23:23:33 +00:00
Dan Gohman 3192ddfeba [WebAssembly] Implement isCheapToSpeculateCtlz and isCheapToSpeculateCttz.
This unbreaks test/CodeGen/WebAssembly/i32.ll and
test/CodeGen/WebAssembly/i64.ll after r224899.

llvm-svn: 253617
2015-11-19 23:04:59 +00:00
Arch D. Robison 6de40c944d Cleanup some -Wundef warnings in include/llvm/Support/MathExtras.h
Fix avoids gratuitous warnings from gcc for "_MSC_VER" not being defined.

Differential Revision: http://reviews.llvm.org/D14598

Patch by Tony Kelman <tony@kelman.net>

llvm-svn: 253614
2015-11-19 22:37:26 +00:00
Diego Novillo 379cc5e71b SamplePGO - Tweak debugging output for function samples. NFC.
llvm-svn: 253612
2015-11-19 22:18:30 +00:00
Simon Pilgrim a9912617c8 [X86][SSE4A] Fix issue with EXTRQI shuffles not starting at the correct start index.
Found during stress testing.

llvm-svn: 253611
2015-11-19 22:13:56 +00:00
Sanjay Patel c4aa50414b [InstCombine] add tests to show missing trunc optimizations
llvm-svn: 253609
2015-11-19 22:11:52 +00:00
Reid Kleckner ebee6129cd Fix UMRs in Mips disassembler on invalid instruction streams
The Insn and Size local variables were used without initialization.

llvm-svn: 253607
2015-11-19 21:51:55 +00:00
Simon Pilgrim ae0140d6ec [X86] Use existing MachineInstrBuilder::addDisp to create offseted pointer. NFC.
Minor code duplication tidyup to D13988

llvm-svn: 253606
2015-11-19 21:50:57 +00:00
Davide Italiano c807f487f7 Follow up to r253591. Turn into an assertion.
Reported by: David Blaikie.

llvm-svn: 253605
2015-11-19 21:50:08 +00:00
Chad Rosier 1cd3da15e8 [LIR] Update some comments. NFC.
llvm-svn: 253603
2015-11-19 21:33:07 +00:00
Sanjay Patel f1c2370c48 [InstCombine] add tests to show missing bitcast optimizations
llvm-svn: 253602
2015-11-19 21:32:25 +00:00
Krzysztof Parzyszek df537b97b1 Expand subregisters in MachineFrameInfo::getPristineRegs
http://reviews.llvm.org/D14719

llvm-svn: 253600
2015-11-19 21:18:52 +00:00
Dehao Chen 014fb55711 Fix the debug build breakage that getDiscriminator is called by mistake.
llvm-svn: 253597
2015-11-19 20:29:27 +00:00
Michael Zolotukhin 6c11c04db3 Revert r253253 and r253126: "Don't recompute LCSSA after loop-unrolling when possible."
The change exposed a bug in IndVarSimplify (PR25578), which led to a
failure (PR25538). When the bug is fixed, this patch can be reapplied.

The tests are kept in tree, as they're useful anyway, and will not break
with this revert.

llvm-svn: 253596
2015-11-19 20:28:32 +00:00
Dehao Chen 23e2278e27 Reimplement discriminator assignment algorithm.
Summary: The new algorithm is more efficient (O(n), n is number of basic blocks). And it is guaranteed to cover all cases of multiple BB mapped to same line.

Reviewers: dblaikie, davidxl, dnovillo

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D14738

llvm-svn: 253594
2015-11-19 19:53:05 +00:00
Davide Italiano 193c4edffb [AddressSanitizer] assert(false) -> llvm_unreachable and remove return.
llvm-svn: 253591
2015-11-19 19:28:23 +00:00
Jun Bum Lim c12c2790e1 [AArch64] Refactoring aarch64-ldst-opt. NCF.
Summary :
 * Rename isSmallTypeLdMerge() to isNarrowLoad().
 * Rename NumSmallTypeMerged to NumNarrowTypePromoted.
 * Use Subtarget defined as a member variable.

llvm-svn: 253587
2015-11-19 18:41:27 +00:00
Chad Rosier 3ecc8d8d83 [LIR] Fix 80-column from previous commit.
llvm-svn: 253586
2015-11-19 18:25:11 +00:00
Chad Rosier fddc01f393 [LIR] Sink checks into function to enable future refactoring. NFC.
The purpose of this change is help delineate the memset and memcpy
optimizations with the overall goal of resolving PR25520.

llvm-svn: 253585
2015-11-19 18:22:21 +00:00
James Molloy 1d695a09dd [GlobalOpt] Localize some globals that have non-instruction users
We currently bail out of global localization if the global has non-instruction users. However, often these can be simple bitcasts or constant-GEPs, which we can easily turn into instructions before localizing. Be a bit more aggressive.

llvm-svn: 253584
2015-11-19 18:04:33 +00:00
Sanjay Patel 2fe7728233 update comment and error message; NFC
'notail' was added in:
http://reviews.llvm.org/rL252368

llvm-svn: 253580
2015-11-19 17:35:55 +00:00
Chad Rosier 85c21f0a6e [LIR] Use the more appropriate method. NFC.
llvm-svn: 253578
2015-11-19 17:27:28 +00:00
Jun Bum Lim 4c35ccac91 [AArch64]Extend merging narrow loads into a wider load
This change extends r251438 to handle more narrow load promotions
including byte type, unscaled, and signed. For example, this change will
convert :
  ldursh w1, [x0, #-2]
  ldurh  w2, [x0, #-4]
into
  ldur  w2, [x0, #-4]
  asr   w1, w2, #16
  and   w2, w2, #0xffff

llvm-svn: 253577
2015-11-19 17:21:41 +00:00
Sanjay Patel ae3680cbcd this new test file was accidentally left out of r253573
llvm-svn: 253574
2015-11-19 16:39:00 +00:00
Sanjay Patel 4699b8ab6a [CGP] despeculate expensive cttz/ctlz intrinsics
This is another step towards allowing SimplifyCFG to speculate harder, but then have 
CGP clean things up if the target doesn't like it.

Previous patches in this series:
http://reviews.llvm.org/D12882
http://reviews.llvm.org/D13297

D13297 should catch most expensive ops, but speculation of cttz/ctlz requires special
handling because of weirdness in the intrinsic definition for handling a zero input 
(that definition can probably be blamed on x86).

For example, if we have the usual speculated-by-select expensive op pattern like this:

  %tobool = icmp eq i64 %A, 0
  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)   ; is_zero_undef == true
  %cond = select i1 %tobool, i64 64, i64 %0
  ret i64 %cond

There's an instcombine that will turn it into:

  %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 false)   ; is_zero_undef == false

This CGP patch is looking for that case and despeculating it back into:

  entry:
    %tobool = icmp eq i64 %A, 0
    br i1 %tobool, label %cond.end, label %cond.true

  cond.true:
    %0 = tail call i64 @llvm.cttz.i64(i64 %A, i1 true)    ; is_zero_undef == true
    br label %cond.end

  cond.end:
    %cond = phi i64 [ %0, %cond.true ], [ 64, %entry ]
    ret i64 %cond

This unfortunately may lead to poorer codegen (see the changes in the existing x86 test), 
but if we increase speculation in SimplifyCFG (the next step in this patch series), then
we should avoid those kinds of cases in the first place.

The need for this patch was originally mentioned here:
http://reviews.llvm.org/D7506
with follow-up here:
http://reviews.llvm.org/D7554

Differential Revision: http://reviews.llvm.org/D14630

llvm-svn: 253573
2015-11-19 16:37:10 +00:00
Hans Wennborg dcc2500452 X86: More efficient legalization of wide integer compares
In particular, this makes the code for 64-bit compares on 32-bit targets
much more efficient.

Example:

  define i32 @test_slt(i64 %a, i64 %b) {
  entry:
    %cmp = icmp slt i64 %a, %b
    br i1 %cmp, label %bb1, label %bb2
  bb1:
    ret i32 1
  bb2:
    ret i32 2
  }

Before this patch:

  test_slt:
          movl    4(%esp), %eax
          movl    8(%esp), %ecx
          cmpl    12(%esp), %eax
          setae   %al
          cmpl    16(%esp), %ecx
          setge   %cl
          je      .LBB2_2
          movb    %cl, %al
  .LBB2_2:
          testb   %al, %al
          jne     .LBB2_4
          movl    $1, %eax
          retl
  .LBB2_4:
          movl    $2, %eax
          retl

After this patch:

  test_slt:
          movl    4(%esp), %eax
          movl    8(%esp), %ecx
          cmpl    12(%esp), %eax
          sbbl    16(%esp), %ecx
          jge     .LBB1_2
          movl    $1, %eax
          retl
  .LBB1_2:
          movl    $2, %eax
          retl

Differential Revision: http://reviews.llvm.org/D14496

llvm-svn: 253572
2015-11-19 16:35:08 +00:00
NAKAMURA Takumi 768579c409 TargetParser.cpp: Fixup -- StringRef::startswith() is better here. NFC.
llvm-svn: 253570
2015-11-19 15:42:52 +00:00
Mehdi Amini 0027c1d21b Remove unused function parameter (NFC)
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 253569
2015-11-19 15:42:34 +00:00
Diego Novillo ef548d2918 SamplePGO - Sort samples by source location when emitting as text.
When dumping function samples or writing them out as text format, it
helps if the samples are emitted sorted by source location. The sorting
of the maps is a bit slow, so we only do it on demand.

llvm-svn: 253568
2015-11-19 15:33:08 +00:00
Zoran Jovanovic 307f80eab1 [mips] Add tests for ROL and ROR macros expansion
Author: obucina
llvm-svn: 253567
2015-11-19 15:04:31 +00:00
NAKAMURA Takumi b6b254582f llvm/lib/Support/TargetParser.cpp: Rework llvm::ARM::getArchExtFeature() to avoid abuse of Twine in r253470.
llvm-svn: 253566
2015-11-19 15:03:11 +00:00
Chad Rosier 33efdf810f [LV] Add a helper function, isReductionVariable. NFC.
llvm-svn: 253565
2015-11-19 14:19:06 +00:00
Zoran Jovanovic 00f998b440 [mips] Expansion of ROL and ROR macros
Author: obucina

Reviewers: dsanders

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D10611

llvm-svn: 253564
2015-11-19 14:15:03 +00:00
Elena Demikhovsky 7c2c9fd243 AVX-512: Fixed COPY_TO_REGCLASS for mask registers
Copying one mask register to another under BW should be done with kmovq instruction, otherwise we can loose some bits.
Copying 8 bits under DQ may be done with kmovb.

Differential Revision: http://reviews.llvm.org/D14812

llvm-svn: 253563
2015-11-19 13:13:00 +00:00
Artyom Skrobov 444d544e9d Removing specific target from the generic test
llvm-svn: 253562
2015-11-19 12:24:47 +00:00
Simon Pilgrim 846b64e17a [X86][AVX] Fix lowering of X86ISD::VZEXT_MOVL for 128-bit -> 256-bit extension
The lowering patterns for X86ISD::VZEXT_MOVL for 128-bit to 256-bit vectors were just copying the lower xmm instead of actually masking off the first scalar using a blend.

Fix for PR25320.

Differential Revision: http://reviews.llvm.org/D14151

llvm-svn: 253561
2015-11-19 12:18:37 +00:00
Alexey Bataev b7b82bf33e Alternative to long nops for X86 CPUs, by Andrey Turetsky
Make X86AsmBackend generate smarter nops instead of a bunch of 0x90 for code alignment for CPUs which don't support long nop instructions.
Differential Revision: http://reviews.llvm.org/D14178

llvm-svn: 253557
2015-11-19 11:44:35 +00:00
Dan Liew 26da45c2bb [lit] Fix bug when using Python3 where a failing test would not show
the script when running a ShTest with an external or internal shell.

This bug is caused by use of the ``map`` function in Python 3 which
returns an iterable (rather than a list in Python 2). After the iterable
is exhausted it won't return any more output and consequently when
``_runShTest()`` tries to access the ``script`` which has already been
iterated over it is empty. Converting to a list immediatley after
calling ``map()`` fixes this.

This fixes the ``tests/shtest-format.py`` test when running under
Python3 which was previously failing.

llvm-svn: 253556
2015-11-19 11:35:42 +00:00
NAKAMURA Takumi b13e63ce08 gold-plugin.cpp: Fix diagnosticHandler corresponding to r253540.
llvm-svn: 253553
2015-11-19 10:43:44 +00:00
James Molloy 0ecdbe7d6b [FunctionAttrs] Provide a mechanism for adding function attributes from the command line
This provides a way to force a function to have certain attributes from the command line. This can be useful when debugging or doing workload exploration, where manually editing IR is tedious or not possible (due to build systems etc).

The syntax is -force-attribute=function_name:attribute_name

All function attributes are parsed except alignstack as it requires an argument.

llvm-svn: 253550
2015-11-19 08:49:57 +00:00
Igor Breger 1f78296869 AVX512: Implemented encoding, intrinsics and DAG lowering for VMOVDDUP instructions.
Differential Revision: http://reviews.llvm.org/D14702

llvm-svn: 253548
2015-11-19 08:26:56 +00:00
Igor Breger 4424aaa28e AVX512: Implemented encoding for the vmovss.s and vmovsd.s instructions.
Differential Revision: http://reviews.llvm.org/D14771

llvm-svn: 253547
2015-11-19 07:58:33 +00:00