ef309c3384
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
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llvm-svn: 142480
2011-10-19 07:48:35 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
0ae8d4d738
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
25ea4e5ad3
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
27ad12539d
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
965de2c197
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
3657fe4b17
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141939
2011-10-14 03:21:46 +00:00
063f55ffdd
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
8cc9388073
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141854
2011-10-13 07:09:14 +00:00
271064e873
Add X86 LZCNT instruction. Including instruction selection support.
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llvm-svn: 141651
2011-10-11 06:44:02 +00:00
a697852386
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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llvm-svn: 141642
2011-10-11 04:34:23 +00:00
fe9179fa4f
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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llvm-svn: 141505
2011-10-09 07:31:39 +00:00
d9cfddc5cd
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
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llvm-svn: 141358
2011-10-07 07:02:24 +00:00
bf136764ae
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
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llvm-svn: 141354
2011-10-07 05:53:50 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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llvm-svn: 141065
2011-10-04 06:30:42 +00:00
786bdb9e14
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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llvm-svn: 141007
2011-10-03 17:28:23 +00:00
0d0be47d03
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
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llvm-svn: 140997
2011-10-03 08:14:29 +00:00
7aea69d949
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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llvm-svn: 140974
2011-10-02 21:08:12 +00:00
21c33657d6
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
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llvm-svn: 140971
2011-10-02 16:56:09 +00:00
d07a59f288
Fix disassembling of INVEPT and INVVPID to take operands
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llvm-svn: 140955
2011-10-01 21:20:14 +00:00
88cb33e0d4
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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llvm-svn: 140954
2011-10-01 19:54:56 +00:00
ee8157cb41
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
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llvm-svn: 139691
2011-09-14 06:41:26 +00:00
96e00e5a24
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
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llvm-svn: 139690
2011-09-14 05:55:28 +00:00
e98d8a5c84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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llvm-svn: 139588
2011-09-13 06:54:58 +00:00
48f2b36911
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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llvm-svn: 139486
2011-09-11 23:19:54 +00:00
a88e356017
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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llvm-svn: 139485
2011-09-11 21:41:45 +00:00
a948cb9058
Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP disassembling to ignore OpSize and REX.W.
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llvm-svn: 139484
2011-09-11 20:23:20 +00:00
5b03f72292
Change X86 disassembly to print immediates values as signed by default. Special
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case those instructions that the immediate is not sign-extend. radr://8795217
llvm-svn: 139028
2011-09-02 20:01:23 +00:00
94ce535647
Make IC_VEX* not inherit from IC_*. Prevents instructions with no VEX form from disassembling to their non-VEX form. Also prevents weak filter collisons that were keeping valid VEX instructions from decoding properly. Make VEX_L* not inherit from VEX_* because the VEX.L bit always important. This stops packed int VEX encodings from being disassembled when specified with VEX.L=1. Fixes PR10831 and PR10806.
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llvm-svn: 138997
2011-09-02 04:17:54 +00:00
4f2fba1108
Add vvvv support to disassembling of instructions with MRMDestMem and MRMDestReg form. Needed to support mem dest form of vmaskmovps/d. Fixes PR10807.
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llvm-svn: 138795
2011-08-30 07:09:35 +00:00
c66d50d1a2
Fix disassembling of VCVTSD2SI
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llvm-svn: 138623
2011-08-26 04:49:29 +00:00
76e3e0b554
Give ATTR_VEX higher priority when generating the disassembler context table. Fixes disassembling of VEX instructions with 'pp'=00. Fixes subset of PR10678.
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llvm-svn: 138552
2011-08-25 07:42:00 +00:00
e1541838f9
Add TB encoding to VEROALL, VZEROUPPER, and VCVTPS2PD to allow them to be disassembled. Fixes PR10723.
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llvm-svn: 138551
2011-08-25 06:57:46 +00:00
ba6c2a52c7
Add TB encoding to VEX versions of SSE fp logical operations to fix disassembler
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llvm-svn: 138034
2011-08-19 05:28:50 +00:00
f2f4837de3
Basic sanity checks to ensure that 2- and 3-byte
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VEX prefixes are working for triadic AVX
instructions. This concludes the patch set to
enable AVX support for the X86 disassebler.
llvm-svn: 127647
2011-03-15 01:32:46 +00:00
2cd8b08207
Segregate tests by target.
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llvm-svn: 119050
2010-11-14 18:14:32 +00:00
Craig Topper