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1767 Commits

Author SHA1 Message Date
Jim Grosbach 11c0b347c6 Assembly parsing for 4-register sequential variant of VLD2. 
llvm-svn: 142704
 2011-10-21 23:58:57 +00:00
Jim Grosbach 118b38cbf1 Assembly parsing for 2-register sequential variant of VLD2. 
llvm-svn: 142691
 2011-10-21 22:21:10 +00:00
Jim Grosbach 846bcff7c7 Assembly parsing for 4-register variant of VLD1. 
llvm-svn: 142682
 2011-10-21 20:35:01 +00:00
Jim Grosbach c4360fe575 Assembly parsing for 3-register variant of VLD1. 
llvm-svn: 142675
 2011-10-21 20:02:19 +00:00
Jim Grosbach 2f2e3c4737 ARM VLD parsing and encoding. 
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.

Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.

llvm-svn: 142670
 2011-10-21 18:54:25 +00:00
Owen Anderson 16c8fc5191 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Owen Anderson 608c60c773 Fix decoding tests for fixed MSR encodings. 
llvm-svn: 142624
 2011-10-20 22:01:48 +00:00
Owen Anderson 48da0ed477 Fix tests for corrected MSR encodings. 
llvm-svn: 142622
 2011-10-20 21:53:19 +00:00
Jim Grosbach 9036c5cf2b ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. 
llvm-svn: 142583
 2011-10-20 15:04:25 +00:00
Jim Grosbach 3ad44e50b3 Tidy up formatting. 
llvm-svn: 142582
 2011-10-20 14:57:47 +00:00
Jim Grosbach 8db25984a9 ARM VTBX (one register) assembly parsing and encoding. 
llvm-svn: 142581
 2011-10-20 14:48:50 +00:00
Rafael Espindola e0d0908356 Fix parsing of a line with only a # in it. 
llvm-svn: 142537
 2011-10-19 18:48:52 +00:00
Craig Topper ef309c3384 Rename PEXTR to PEXT. Add intrinsics for BMI instructions. 
llvm-svn: 142480
 2011-10-19 07:48:35 +00:00
Jim Grosbach 43f1d206b9 Tidy up formatting. 
llvm-svn: 142422
 2011-10-18 21:09:01 +00:00
Jim Grosbach 1f63e04b2c Tidy up formatting. 
llvm-svn: 142421
 2011-10-18 21:08:16 +00:00
Jim Grosbach 4e5c764b65 Enable more encoded immediate tests. 
llvm-svn: 142415
 2011-10-18 20:20:51 +00:00
Jim Grosbach 89f9e1dca4 More vmov lane testcases. 
llvm-svn: 142414
 2011-10-18 20:19:48 +00:00
Jim Grosbach e9f204c197 ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142413
 2011-10-18 20:14:56 +00:00
Jim Grosbach 712f3670fd ARM vmov assembly parsing for the lane index operand. 
llvm-svn: 142412
 2011-10-18 20:10:47 +00:00
Jim Grosbach 611450071c ARM vmla/vmls assembly parsing for the lane index operand. 
llvm-svn: 142389
 2011-10-18 18:27:07 +00:00
Owen Anderson 40ec1da2ab Another failing encoding. 
llvm-svn: 142388
 2011-10-18 18:23:03 +00:00
Jim Grosbach 32b83a4e16 Fix NEON mul encoding tests. Wrong file contents previously. 
llvm-svn: 142387
 2011-10-18 18:14:55 +00:00
Jim Grosbach c8eff0327a ARM vqdmulh assembly parsing for the lane index operand. 
llvm-svn: 142386
 2011-10-18 18:12:09 +00:00
Jim Grosbach d1bc6da657 Remove duplicate test. 
llvm-svn: 142383
 2011-10-18 18:05:50 +00:00
Jim Grosbach b3ecff77cd Tidy up formatting. 
llvm-svn: 142382
 2011-10-18 18:05:16 +00:00
Jim Grosbach e6fbca3a61 ARM vmul assembly parsing for the lane index operand. 
llvm-svn: 142381
 2011-10-18 18:01:52 +00:00
Jim Grosbach f416cb16c0 Tidy up. 
llvm-svn: 142380
 2011-10-18 18:01:09 +00:00
Owen Anderson c91064551a Add a few more testcases. 
llvm-svn: 142379
 2011-10-18 17:57:31 +00:00
Owen Anderson 2a498c1107 Add several FIXME cases for ARM encodings. 
llvm-svn: 142377
 2011-10-18 17:50:22 +00:00
Jim Grosbach 8206790ab0 Tests for 142365. 
llvm-svn: 142368
 2011-10-18 17:23:34 +00:00
Jim Grosbach 95135982cd Tidy up formatting. 
llvm-svn: 142367
 2011-10-18 17:22:53 +00:00
Jim Grosbach e4454e0de2 ARM assembly parsing and encoding for VMOV.i64. 
llvm-svn: 142356
 2011-10-18 16:18:11 +00:00
Jim Grosbach 8211c051ca ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32. 
llvm-svn: 142321
 2011-10-18 00:22:00 +00:00
Jim Grosbach 26bfc9e5da Enable a few more NEON immediate tests. 
llvm-svn: 142313
 2011-10-17 23:50:19 +00:00
Jim Grosbach cda32ae372 ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16. 
llvm-svn: 142303
 2011-10-17 23:09:09 +00:00
Nick Lewycky 40f8f2ff24 Add support for a new extension to the .file directive: 
.file filenumber "directory" "filename"

This removes one join+split of the directory+filename in MC internals. Because
bitcode files have independent fields for directory and filenames in debug info,
this patch may change the .o files written by existing .bc files.

llvm-svn: 142300
 2011-10-17 23:05:28 +00:00
Jim Grosbach 741cd73aab ARM NEON "vmov.i8" immediate assembly parsing and encoding. 
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.

llvm-svn: 142293
 2011-10-17 22:26:03 +00:00
Craig Topper 96fa597828 Add X86 PEXTR and PDEP instructions. 
llvm-svn: 142141
 2011-10-16 16:50:08 +00:00
Craig Topper aea148c366 Add X86 BZHI instruction as well as BMI2 feature detection. 
llvm-svn: 142122
 2011-10-16 07:55:05 +00:00
Craig Topper 0ae8d4d738 Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. 
llvm-svn: 142117
 2011-10-16 07:05:40 +00:00
Chris Lattner a3a0681083 Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance 
the X86 asmparser to produce ranges in the one case that was annoying me, for example:

test.s:10:15: error: invalid operand for instruction
movl 0(%rax), 0(%edx)
              ^~~~~~~

It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use 
ranges where appropriate if someone is interested.

llvm-svn: 142106
 2011-10-16 04:47:35 +00:00
Craig Topper 25ea4e5ad3 Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen 
llvm-svn: 142105
 2011-10-16 03:51:13 +00:00
Craig Topper 27ad12539d Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension. 
llvm-svn: 142082
 2011-10-15 20:46:47 +00:00
Owen Anderson 220f2643fa Update test for disabling of code/data marker labels in ELF. 
llvm-svn: 142003
 2011-10-14 21:12:55 +00:00
Craig Topper 965de2c197 Add X86 ANDN instruction. Including instruction selection. 
llvm-svn: 141947
 2011-10-14 07:06:56 +00:00
Craig Topper 3657fe4b17 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141939
 2011-10-14 03:21:46 +00:00
Bill Wendling 063f55ffdd Revert r141854 because it was causing failures: 
http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101

--- Reverse-merging r141854 into '.':
U    test/MC/Disassembler/X86/x86-32.txt
U    test/MC/Disassembler/X86/simple-tests.txt
D    test/CodeGen/X86/bmi.ll
U    lib/Target/X86/X86InstrInfo.td
U    lib/Target/X86/X86ISelLowering.cpp
U    lib/Target/X86/X86.td
U    lib/Target/X86/X86Subtarget.h

llvm-svn: 141857
 2011-10-13 07:48:07 +00:00
Craig Topper 8cc9388073 Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell. 
llvm-svn: 141854
 2011-10-13 07:09:14 +00:00
Kevin Enderby e7c0c499b8 Finish supporting cpp #file/line comments in assembler for error messages. So 
for cpp pre-processed assembly we give correct filename and line numbers when
reporting errors in assembly files when using clang and -integrated-as on .s
files. rdar://8998895

llvm-svn: 141814
 2011-10-12 21:38:39 +00:00
Jim Grosbach 54a20ed0f1 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00