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9763 Commits

Author SHA1 Message Date
Andrew Lenharth 740f93ca10 Get rid of idefs for arguments (oops) 
llvm-svn: 21251
 2005-04-12 17:47:57 +00:00
Andrew Lenharth 10c6eb4be2 Get rid of idefs for arguments 
llvm-svn: 21250
 2005-04-12 17:35:16 +00:00
Chris Lattner 14f72885dd Put out* into the allocation order, allowing the register allocator to 
coallesce moves into outgoing args.

llvm-svn: 21249
 2005-04-12 15:12:51 +00:00
Chris Lattner 6b91767b77 Make sure to realize that calls use their argument regs 
llvm-svn: 21248
 2005-04-12 15:12:19 +00:00
Duraid Madina b6dfb227b7 stop emitting IDEFs for args - change to using liveIn/liveOut 
llvm-svn: 21247
 2005-04-12 14:54:44 +00:00
Nate Begeman f67f3bf627 Initial support for allocation condition registers 
llvm-svn: 21246
 2005-04-12 07:04:16 +00:00
Chris Lattner 6febe5ef40 Fix a crash analyzing MultiSource/Benchmarks/MallocBench/gs 
llvm-svn: 21245
 2005-04-12 03:59:27 +00:00
Chris Lattner af5b25f139 Remove some redundant checks, add a couple of new ones. This allows us to 
compile this:

int foo (unsigned long a, unsigned long long g) {
  return a >= g;
}

To:

foo:
        movl 8(%esp), %eax
        cmpl %eax, 4(%esp)
        setae %al
        cmpl $0, 12(%esp)
        sete %cl
        andb %al, %cl
        movzbl %cl, %eax
        ret

instead of:

foo:
        movl 8(%esp), %eax
        cmpl %eax, 4(%esp)
        setae %al
        movzbw %al, %cx
        movl 12(%esp), %edx
        cmpl $0, %edx
        sete %al
        movzbw %al, %ax
        cmpl $0, %edx
        cmove %cx, %ax
        movzbl %al, %eax
        ret

llvm-svn: 21244
 2005-04-12 02:54:39 +00:00
Chris Lattner aedcabe8db Emit comparisons against the sign bit better. Codegen this: 
bool %test1(long %X) {
        %A = setlt long %X, 0
        ret bool %A
}

like this:

test1:
        cmpl $0, 8(%esp)
        setl %al
        movzbl %al, %eax
        ret

instead of:

test1:
        movl 8(%esp), %ecx
        cmpl $0, %ecx
        setl %al
        movzbw %al, %ax
        cmpl $0, 4(%esp)
        setb %dl
        movzbw %dl, %dx
        cmpl $0, %ecx
        cmove %dx, %ax
        movzbl %al, %eax
        ret

llvm-svn: 21243
 2005-04-12 02:19:10 +00:00
Chris Lattner 71ff44e46c Emit long comparison against -1 better. Instead of this (x86): 
test2:
        movl 8(%esp), %eax
        notl %eax
        movl 4(%esp), %ecx
        notl %ecx
        orl %eax, %ecx
        cmpl $0, %ecx
        sete %al
        movzbl %al, %eax
        ret

or this (PPC):

_test2:
        nor r2, r4, r4
        nor r3, r3, r3
        or r2, r2, r3
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

Emit this:

test2:
        movl 8(%esp), %eax
        andl 4(%esp), %eax
        cmpl $-1, %eax
        sete %al
        movzbl %al, %eax
        ret

or this:

_test2:
.LBB_test2_0:   ;
        and r2, r4, r3
        cmpwi cr0, r2, -1
        li r3, 1
        li r2, 0
        beq .LBB_test2_2        ;
.LBB_test2_1:   ;
        or r3, r2, r2
.LBB_test2_2:   ;
        blr

it seems like the PPC isel could do better for R32 == -1 case.

llvm-svn: 21242
 2005-04-12 01:46:05 +00:00
Chris Lattner 87bd69884a canonicalize x <u 1 -> x == 0. On this testcase: 
unsigned long long g;
unsigned long foo (unsigned long a) {
  return (a >= g) ? 1 : 0;
}

It changes the ppc code from:

_foo:
.LBB_foo_0:     ; entry
        mflr r11
        stw r11, 8(r1)
        bl "L00000$pb"
"L00000$pb":
        mflr r2
        addis r2, r2, ha16(L_g$non_lazy_ptr-"L00000$pb")
        lwz r2, lo16(L_g$non_lazy_ptr-"L00000$pb")(r2)
        lwz r4, 0(r2)
        lwz r2, 4(r2)
        cmplw cr0, r3, r2
        li r2, 1
        li r3, 0
        bge .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        or r2, r3, r3
.LBB_foo_2:     ; entry
        cmplwi cr0, r4, 1
        li r3, 1
        li r5, 0
        blt .LBB_foo_4  ; entry
.LBB_foo_3:     ; entry
        or r3, r5, r5
.LBB_foo_4:     ; entry
        cmpwi cr0, r4, 0
        beq .LBB_foo_6  ; entry
.LBB_foo_5:     ; entry
        or r2, r3, r3
.LBB_foo_6:     ; entry
        rlwinm r3, r2, 0, 31, 31
        lwz r11, 8(r1)
        mtlr r11
        blr


to:

_foo:
.LBB_foo_0:     ; entry
        mflr r11
        stw r11, 8(r1)
        bl "L00000$pb"
"L00000$pb":
        mflr r2
        addis r2, r2, ha16(L_g$non_lazy_ptr-"L00000$pb")
        lwz r2, lo16(L_g$non_lazy_ptr-"L00000$pb")(r2)
        lwz r4, 0(r2)
        lwz r2, 4(r2)
        cmplw cr0, r3, r2
        li r2, 1
        li r3, 0
        bge .LBB_foo_2  ; entry
.LBB_foo_1:     ; entry
        or r2, r3, r3
.LBB_foo_2:     ; entry
        cntlzw r3, r4
        srwi r3, r3, 5
        cmpwi cr0, r4, 0
        beq .LBB_foo_4  ; entry
.LBB_foo_3:     ; entry
        or r2, r3, r3
.LBB_foo_4:     ; entry
        rlwinm r3, r2, 0, 31, 31
        lwz r11, 8(r1)
        mtlr r11
        blr

llvm-svn: 21241
 2005-04-12 00:28:49 +00:00
Nate Begeman 79a3bea4ca Implement bitfield clears 
Implement divide by negative power of two

llvm-svn: 21240
 2005-04-12 00:10:02 +00:00
Nate Begeman 08698cf644 Update PPC readme. Remove things that are done or aren't ppc specific 
llvm-svn: 21232
 2005-04-11 20:48:57 +00:00
Chris Lattner 8ffd004920 Teach the dag mechanism that this: 
long long test2(unsigned A, unsigned B) {
        return ((unsigned long long)A << 32) + B;
}

is equivalent to this:

long long test1(unsigned A, unsigned B) {
        return ((unsigned long long)A << 32) | B;
}

Now they are both codegen'd to this on ppc:

_test2:
        blr

or this on x86:

test2:
        movl 4(%esp), %edx
        movl 8(%esp), %eax
        ret

llvm-svn: 21231
 2005-04-11 20:29:59 +00:00
Chris Lattner edd197062f Fix expansion of shifts by exactly NVT bits on arch's (like X86) that have 
masking shifts.

This fixes the miscompilation of this:

long long test1(unsigned A, unsigned B) {
        return ((unsigned long long)A << 32) | B;
}

into this:

test1:
        movl 4(%esp), %edx
        movl %edx, %eax
        orl 8(%esp), %eax
        ret

allowing us to generate this instead:

test1:
        movl 4(%esp), %edx
        movl 8(%esp), %eax
        ret

llvm-svn: 21230
 2005-04-11 20:08:52 +00:00
Chris Lattner 607bd26b38 IA64 supports this operation. 
llvm-svn: 21228
 2005-04-11 18:55:36 +00:00
Chris Lattner 67291ea580 ORo sets CR0 
llvm-svn: 21227
 2005-04-11 15:03:48 +00:00
Chris Lattner f29cc88210 Revert the previous patch, which I didn't mean to check in. 
llvm-svn: 21226
 2005-04-11 15:03:41 +00:00
Chris Lattner d3dc31009f Fix a minor bug (ORo didn't mark that it set CR0). 
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225
 2005-04-11 15:01:39 +00:00
Duraid Madina 8de7ac092d hmm, should probably change addImm() to take 64-bit arguments one day anyway. 
llvm-svn: 21224
 2005-04-11 07:16:39 +00:00
Nate Begeman bebefac791 Add recording variants of ISD::AND and ISD::OR. This kills almost 1000 
(1.5%) instructions in 186.crafty

llvm-svn: 21222
 2005-04-11 06:34:10 +00:00
Duraid Madina fb43ef78c5 assorted fixes: 
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.

llvm-svn: 21221
 2005-04-11 05:55:56 +00:00
Jeff Cohen a3b1458175 Eliminate tabs 
llvm-svn: 21216
 2005-04-11 03:44:22 +00:00
Nate Begeman add0c63ad2 Fix libcall code to not pass a NULL Chain to LowerCallTo 
Fix libcall code to not crash or assert looking for an ADJCALLSTACKUP node
  when it is known that there is no ADJCALLSTACKDOWN to match.
Expand i64 multiply when ISD::MULHU is legal for the target.

llvm-svn: 21214
 2005-04-11 03:01:51 +00:00
Chris Lattner e2427c9afc Don't bother sign/zext_inreg'ing the result of an and operation if we know 
the result does change as a result of the extend.

This improves codegen for Alpha on this testcase:

int %a(ushort* %i) {
        %tmp.1 = load ushort* %i
        %tmp.2 = cast ushort %tmp.1 to int
        %tmp.4 = and int %tmp.2, 1
        ret int %tmp.4
}

Generating:

a:
        ldgp $29, 0($27)
        ldwu $0,0($16)
        and $0,1,$0
        ret $31,($26),1

instead of:

a:
        ldgp $29, 0($27)
        ldwu $0,0($16)
        and $0,1,$0
        addl $0,0,$0
        ret $31,($26),1

btw, alpha really should switch to livein/outs for args :)

llvm-svn: 21213
 2005-04-10 23:37:16 +00:00
Chris Lattner a3b7ef05f4 Teach legalize to deal with targets that don't support some SEXTLOAD/ZEXTLOADs 
llvm-svn: 21212
 2005-04-10 22:54:25 +00:00
Chris Lattner 391a351ede don't zextload fp values! 
llvm-svn: 21209
 2005-04-10 17:40:35 +00:00
Nate Begeman 492370311d Fix another fixme: factor out the constant fp generation code. 
llvm-svn: 21207
 2005-04-10 06:06:10 +00:00
Nate Begeman 941a01802f Fix 64 bit argument loading that straddles the args in regs / args on stack 
boundary.

llvm-svn: 21206
 2005-04-10 05:53:14 +00:00
Chris Lattner c53cd501b5 Until we have a dag combiner, promote using zextload's instead of extloads. 
This gives the optimizer a bit of information about the top-part of the
value.

llvm-svn: 21205
 2005-04-10 04:33:47 +00:00
Chris Lattner f74c794ccf Fold zext_inreg(zextload), likewise for sext's 
llvm-svn: 21204
 2005-04-10 04:33:08 +00:00
Chris Lattner f2bff92411 add a simple xform 
llvm-svn: 21203
 2005-04-10 04:04:49 +00:00
Nate Begeman b076731713 Remove unnecessary Implicit Defs. Since r0 is not in allocation, we do not 
have to inform the register allocator it might be stepped on.

llvm-svn: 21202
 2005-04-10 03:59:42 +00:00
Nate Begeman 6566e8ac06 Make sure that BRCOND branches can be converted into long branches too. 
llvm-svn: 21198
 2005-04-10 01:48:29 +00:00
Nate Begeman 3345eadc37 Don't hand ISD::CALL nodes off to SelectExprFP. This fixes siod. 
llvm-svn: 21197
 2005-04-10 01:14:13 +00:00
Chris Lattner d8cbfe82ba Fix a thinko. If the operand is promoted, pass the promoted value into 
the new zero extend, not the original operand.  This fixes cast bool -> long
on ppc.

Add an unrelated fixme

llvm-svn: 21196
 2005-04-10 01:13:15 +00:00
Chris Lattner 9ff4b4190f rename getPPCOpcodeForSetCCNumber -> getPPCOpcodeForSetCCOpode to be more 
correct.  Remove the EmitComparison retvalue, as it is always the first arg.

Fix a place where we incorrectly passed in the setcc opcode instead of the
setcc number, causing us to miscompile crafty.  Crafty now works!

llvm-svn: 21195
 2005-04-10 01:03:31 +00:00
Nate Begeman 2121a54868 fix ISD::BRCONDTWOWAY codegen to not deference the end() iterator 
llvm-svn: 21193
 2005-04-09 23:35:05 +00:00
Chris Lattner 228fed92e6 Fix CodeGen/Generic/2005-05-09-GlobalInPHI.ll, which was reduced from 254.gap. 
This caused the "use before a def" assertion on some programs.

With this patch, 254.gap now passes with the PPC backend.

llvm-svn: 21191
 2005-04-09 22:05:17 +00:00
Chris Lattner da504741da add a little peephole optimization. This allows us to codegen: 
int a(short i) {
        return i & 1;
}

as

_a:
        andi. r3, r3, 1
        blr

instead of:

_a:
        rlwinm r2, r3, 0, 16, 31
        andi. r3, r2, 1
        blr

on ppc.  It should also help the other risc targets.

llvm-svn: 21189
 2005-04-09 21:43:54 +00:00
Chris Lattner e8e070dbfb do not set the root to null if an argument is dead 
llvm-svn: 21188
 2005-04-09 21:23:24 +00:00
Nate Begeman 8309a333dd Add rlwnm instruction for variable rotate 
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality

llvm-svn: 21187
 2005-04-09 20:09:12 +00:00
Chris Lattner 3a7f5768c5 Fix a crash on 173.applu by asking for a constant bigger than 32-bits. 
llvm-svn: 21185
 2005-04-09 19:47:21 +00:00
Chris Lattner a55a5f2580 Switch this instruction selector over to using liveins and liveouts, eliminating 
implicit defs on entry to the function.  yaay :)

llvm-svn: 21184
 2005-04-09 16:32:30 +00:00
Chris Lattner 1a44855f8f there is no need to remove this instruction, linscan does it already as it 
removes noop moves.

llvm-svn: 21183
 2005-04-09 16:24:20 +00:00
Chris Lattner 0b1681bce1 Adjust live intervals to support a livein set 
llvm-svn: 21182
 2005-04-09 16:17:50 +00:00
Chris Lattner b59006c4a1 Use live out sets for return values instead of imp_defs, which is cleaner and faster. 
llvm-svn: 21181
 2005-04-09 15:23:56 +00:00
Chris Lattner 4c6ab01a20 Consider the livein/out set for a function, allowing targets to not have to 
use ugly imp_def/imp_uses for arguments and return values.

llvm-svn: 21180
 2005-04-09 15:23:25 +00:00
Duraid Madina 46aa06cfed ok, the "ia64 has a boatload of registers" joke stopped being funny today ;) 
* fix overallocation of integer (stacked) registers: we can't allocate
  registers for local use if they are required as output registers

this fixes 'toast' in the test suite, and all sorts of larger programs
like bzip2 etc.

llvm-svn: 21178
 2005-04-09 11:53:00 +00:00
Nate Begeman 2f64122319 Optimize FSEL a bit for fneg arguments. This fixes the recently added test 
case so that we emit

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fsel f1, f1, f3, f2
        blr

instead of:

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fneg f0, f1
        fneg f0, f0
        fsel f1, f0, f3, f2
        blr

llvm-svn: 21177
 2005-04-09 09:33:07 +00:00