Commit Graph

45 Commits

Author SHA1 Message Date
Akira Hatanaka 65ce931f9a Add flags and feature bits for mips dsp.
llvm-svn: 164428
2012-09-21 23:41:49 +00:00
Akira Hatanaka ad4950258b Add register Mips::GP to the list of reserved registers if target is bare-metal
to prevent it from being clobbered. mips uses $gp to access small data section.

This bug was originally reported by Carl Norum.

llvm-svn: 162340
2012-08-22 03:18:13 +00:00
Akira Hatanaka 89d50b3957 Add Android ABI to Mips backend to handle functions returning vectors of four
floats.

llvm-svn: 162008
2012-08-16 03:48:05 +00:00
Akira Hatanaka cdf4fd8267 This patch adds a predicate to existing mips32 and mips64 so that those
instruction encodings can be excluded during mips16 processing.

This revision fixes the issue raised by Jim Grosbach.

bool hasStandardEncoding() const { return !inMips16Mode(); }

When micromips is added it will be

bool StandardEncoding() const { return !inMips16Mode()&&  !inMicroMipsMode(); }

No additional testing is needed other than to assure that there is no regression
from this patch.

Patch by Reed Kotler.

llvm-svn: 157234
2012-05-22 03:10:09 +00:00
Akira Hatanaka 0faaebf27c This patch adds the register class for MIPS16 as well as the ability for
llc to recognize MIPS16 as a MIPS ASE extension. -mips16 will mean the
mips16 ASE for mips32 by default.

As part of fixing of adding this we discovered some small changes that
need to be made to MipsInstrInfo::storeRegToStackSLot and
MipsInstrInfo::loadRegFromStackSlot. We were using some "==" equality tests
where in fact we should have been using Mips::<regclas>.hasSubClassEQ instead,
per suggestion of Jakob Stoklund Olesen.

Patch by Reed Kotler.

llvm-svn: 156958
2012-05-16 22:19:56 +00:00
Akira Hatanaka 047473e293 Turn on post register allocation scheduler.
llvm-svn: 153554
2012-03-28 00:24:17 +00:00
Jia Liu f54f60f3ce remove blanks, and some code format
llvm-svn: 151625
2012-02-28 07:46:26 +00:00
Akira Hatanaka 330d901ce3 Add support for floating point base register + offset register addressing mode
load and store instructions.

llvm-svn: 151611
2012-02-28 02:55:02 +00:00
David Blaikie a379b18173 Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
Akira Hatanaka 6de4d12120 Set ABI if it hasn't been set on the command line.
Check if architecture & ABI combination is valid.

llvm-svn: 140230
2011-09-21 02:45:29 +00:00
Akira Hatanaka 6e506eb57d Fix typo.
llvm-svn: 140229
2011-09-21 02:24:25 +00:00
Akira Hatanaka bb49e721b8 Change the names of functions isMips* to hasMips*.
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
Akira Hatanaka 2b37261fd6 Initial Mips64 support. Patch by Liu with some modifications.
llvm-svn: 140178
2011-09-20 20:28:08 +00:00
Akira Hatanaka 3efff6c9f8 Add comment.
llvm-svn: 139699
2011-09-14 17:22:51 +00:00
Akira Hatanaka 8b983d9773 O64 will not be supported.
llvm-svn: 139421
2011-09-09 22:22:48 +00:00
Akira Hatanaka 4444daeec5 Drop support for Mips1 and Mips2.
llvm-svn: 139405
2011-09-09 20:45:50 +00:00
Evan Cheng 1a72add615 Compute feature bits at time of MCSubtargetInfo initialization.
llvm-svn: 134606
2011-07-07 07:07:08 +00:00
Evan Cheng c9c090d7a5 Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
llvm-svn: 134281
2011-07-01 22:36:09 +00:00
Evan Cheng 0d639a28aa Rename TargetSubtarget to TargetSubtargetInfo for consistency.
llvm-svn: 134259
2011-07-01 21:01:15 +00:00
Evan Cheng 54b68e3432 - Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

llvm-svn: 134257
2011-07-01 20:45:01 +00:00
Evan Cheng fe6e405e8c Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.

The fix is to just have the clients explictly pass the CPU name!

llvm-svn: 134127
2011-06-30 01:53:36 +00:00
Evan Cheng 8264e272a9 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
llvm-svn: 134049
2011-06-29 01:14:12 +00:00
Akira Hatanaka e24891251c Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
llvm-svn: 129612
2011-04-15 21:51:11 +00:00
Akira Hatanaka aef55c8801 Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
llvm-svn: 129606
2011-04-15 21:00:26 +00:00
Bruno Cardoso Lopes ed874eff93 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
llvm-svn: 127003
2011-03-04 17:51:39 +00:00
Bruno Cardoso Lopes 03c0330176 Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>
llvm-svn: 118864
2010-11-12 00:38:32 +00:00
Bruno Cardoso Lopes 9c656fe815 Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka (ahatanaka@mips.com)
llvm-svn: 118447
2010-11-08 21:42:32 +00:00
Douglas Gregor 740ab38bb7 Fix a bunch of little errors that Clang complains about when its being pedantic
llvm-svn: 91764
2009-12-19 07:05:23 +00:00
Chris Lattner 68535f7603 reintroduce support for Mips "small" section handling. This is
implemented somewhat differently than before, but it should have
the same functionality and the previous testcase passes again.

llvm-svn: 78900
2009-08-13 06:28:06 +00:00
Chris Lattner 58e8be847c Restore some "small section" support code, reverting my patch from r76936.
llvm-svn: 78894
2009-08-13 05:41:27 +00:00
Eli Friedman 57c11da8df Remove -disable-mips-abicall and -enable-mips-absolute-call command-line
options, which don't appear to be useful.  -enable-mips-absolute-call is
completely unused (and unless I'm mistaken, is supposed to have the 
same effect that -relocation-model=dynamic-no-pic should have), 
and -disable-mips-abicall appears to be effectively a 
synonym for -relocation-model=static. Adjust the few users of hasABICall
to checks which seem more appropriate.  Update MipsSubtarget, 
MipsTargetMachine, and MipselTargetMachine to synchronize with recent 
changes.

llvm-svn: 77938
2009-08-03 02:22:28 +00:00
Daniel Dunbar 31b44e8f6c Normalize Subtarget constructors to take a target triple string instead of
Module*.

Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.

llvm-svn: 77918
2009-08-02 22:11:08 +00:00
Chris Lattner bc63d8bfbf remove more remnants of small section support.
llvm-svn: 76936
2009-07-24 03:14:35 +00:00
Bruno Cardoso Lopes a72a505a80 Added support for fround, fextend and FP_TO_SINT
llvm-svn: 72483
2009-05-27 17:23:44 +00:00
Anton Korobeynikov 08bf4c0f5a Propagate CPU string out of SubtargetFeatures
llvm-svn: 72335
2009-05-23 19:50:50 +00:00
Bruno Cardoso Lopes f714e25f7e Added new features to represent specific instructions groups
llvm-svn: 54213
2008-07-30 17:01:06 +00:00
Bruno Cardoso Lopes e5d1fcfe4e Added initial support for small sections on Mips.
Added gp_rel relocations to support addressing small section contents.
Added command line to specify small section threshold in bytes.

llvm-svn: 53869
2008-07-21 18:52:34 +00:00
Bruno Cardoso Lopes 80ab8f9649 Added Subtarget support into RegisterInfo
Added HasABICall and HasAbsoluteCall (equivalent to gcc -mabicall and 
-mno-shared). HasAbsoluteCall is not implemented but HasABICall is the 
default for o32 ABI. Now, both should help into a more accurate 
relocation types implementation. 
Added IsLinux is needed to choose between asm directives.
Instruction name strings cleanup.
AsmPrinter improved.

llvm-svn: 53551
2008-07-14 14:42:54 +00:00
Bruno Cardoso Lopes bcc2139ba6 Fixed features usage.
llvm-svn: 53277
2008-07-09 05:32:22 +00:00
Bruno Cardoso Lopes 7ceec57703 Fixe typos and 80 column size problems
llvm-svn: 53272
2008-07-09 04:45:36 +00:00
Bruno Cardoso Lopes c9c3f49993 Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
  yet, but they allow the future inclusion of features easier. Among new features,
  we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
  integer
  and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
  aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
  sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
  FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
  FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
  return copy, no homing location within EABI, non 32-bit stack objects
  arguments, and asm constraint for float.

llvm-svn: 53146
2008-07-05 19:05:21 +00:00
Bruno Cardoso Lopes 326a03732e Some Mips minor fixes
Added support for mips little endian arch => mipsel

llvm-svn: 51923
2008-06-04 01:45:25 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes 87beec9afb InstrItineraryData support on added.
Added Mips3 ISA feature (needed when supporting R4000 machines)

llvm-svn: 41151
2007-08-18 01:52:27 +00:00
Bruno Cardoso Lopes 35e43c49b0 Initial Mips support, here we go! =)
- Modifications from the last patch included
  (issues pointed by Evan Cheng are now fixed).
- Added more MipsI instructions.
- Added more patterns to match branch instructions.

llvm-svn: 37461
2007-06-06 07:42:06 +00:00