Commit Graph

173 Commits

Author SHA1 Message Date
Evan Cheng b8654202dd Backing out 48911 for now. It's breaking stuff.
llvm-svn: 48922
2008-03-28 17:49:06 +00:00
Evan Cheng 9ae4d7b719 Load from stub is already re-materializable.
llvm-svn: 48911
2008-03-28 06:49:25 +00:00
Evan Cheng 308e564693 Code clean up.
llvm-svn: 48856
2008-03-27 01:45:11 +00:00
Evan Cheng 29e62a59f3 Allow certain lea instructions to be rematerialized.
llvm-svn: 48855
2008-03-27 01:41:09 +00:00
Evan Cheng 4fb07c6500 Remove an unused command line option.
llvm-svn: 48854
2008-03-27 01:30:24 +00:00
Dan Gohman 883cbfd0ba Add CMP32mr and friends to the load-unfolding table. Among
other things, this allows the scheduler to unfold a load operand
in the 2008-01-08-SchedulerCrash.ll testcase, so it now successfully
clones the comparison to avoid a pushf+popf.

llvm-svn: 48777
2008-03-25 16:53:19 +00:00
Chris Lattner 5abbe6cef5 Add support for calls that return two FP values in
ST(0)/ST(1).

llvm-svn: 48634
2008-03-21 06:38:26 +00:00
Christopher Lamb d3d0ad3f58 Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register.
llvm-svn: 48412
2008-03-16 03:12:01 +00:00
Christopher Lamb dd55d3f1b2 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects.
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
2008-03-13 05:47:01 +00:00
Chris Lattner 7b27ccfd5e coalesce away 80-bit floating point copies.
llvm-svn: 48241
2008-03-11 19:30:09 +00:00
Chris Lattner 7930d8e775 convert a massive if statement to a switch.
llvm-svn: 48240
2008-03-11 19:28:17 +00:00
Christopher Lamb 342e4104d3 Missed part of recommit.
llvm-svn: 48224
2008-03-11 10:27:36 +00:00
Chris Lattner a4fa0ad30d abort with an assert instead of a cerr to get line#
llvm-svn: 48199
2008-03-10 23:56:08 +00:00
Evan Cheng d4e1d9eeb2 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.
llvm-svn: 48167
2008-03-10 19:31:26 +00:00
Christopher Lamb 4ba3f0430b Allow insert_subreg into implicit, target-specific values.
Change insert/extract subreg instructions to be able to be used in TableGen patterns.
Use the above features to reimplement an x86-64 pseudo instruction as a pattern.

llvm-svn: 48130
2008-03-10 06:12:08 +00:00
Chris Lattner 86829f0ff7 teach X86InstrInfo::copyRegToReg how to copy into ST(0) from
an RFP register class.

Teach ScheduleDAG how to handle CopyToReg with different src/dst 
reg classes.

This allows us to compile trivial inline asms that expect stuff
on the top of x87-fp stack.

llvm-svn: 48107
2008-03-09 09:15:31 +00:00
Chris Lattner b79bafcec8 add some code to support cross-register class copying from
RST -> RFP{32/64/80}.  We only handle ST(0) for now.

llvm-svn: 48104
2008-03-09 08:46:19 +00:00
Chris Lattner c4c9dde04c rearrange some code, no functionality change.
llvm-svn: 48101
2008-03-09 07:58:04 +00:00
Evan Cheng 42cb72e52c Turning on remat of pic loads.
llvm-svn: 47524
2008-02-23 02:07:42 +00:00
Evan Cheng 4d17671997 No need recognize load from a fixed argument slot as re-materializable. LiveIntervalAnalysis already handles it as a special case.
llvm-svn: 47522
2008-02-23 01:47:44 +00:00
Evan Cheng 94ba37f8e3 Allow re-materialization of pic load (controlled by -remat-pic-load for now).
llvm-svn: 47476
2008-02-22 09:25:47 +00:00
Evan Cheng 244183ef0d commuteInstr() can now commute non-ssa machine instrs.
llvm-svn: 47043
2008-02-13 02:46:49 +00:00
Evan Cheng 3b3286d4bc It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Evan Cheng 8d59dd119b Added missing entries in X86 load / store folding tables.
llvm-svn: 46866
2008-02-08 00:12:56 +00:00
Evan Cheng 1bc1cae318 In some cases, e.g. ADD32ri, no transformation is made. Guide against it.
llvm-svn: 46849
2008-02-07 08:29:53 +00:00
Chris Lattner 18df33d0c8 fix a wordo that gordon noticed :)
llvm-svn: 45896
2008-01-12 00:53:16 +00:00
Chris Lattner 6da61c2515 Any x86 instruction that reads from an invariant location is invariant.
This allows us to sink things like:
	cvtsi2sd	32(%esp), %xmm1
when reading from the argument area, for example.

llvm-svn: 45895
2008-01-12 00:35:08 +00:00
Chris Lattner 596875118c rename MachineInstr::setInstrDescriptor -> setDesc
llvm-svn: 45871
2008-01-11 18:10:50 +00:00
Chris Lattner 806dd0e2ac remove xchg and shift-reg-by-1 instructions, which are dead.
llvm-svn: 45870
2008-01-11 18:00:50 +00:00
Chris Lattner c8226f32e9 Simplify the side effect stuff a bit more and make licm/sinking
both work right according to the new flags.

This removes the TII::isReallySideEffectFree predicate, and adds
TII::isInvariantLoad. 

It removes NeverHasSideEffects+MayHaveSideEffects and adds
UnmodeledSideEffects as machine instr flags.  Now the clients
can decide everything they need.

I think isRematerializable can be implemented in terms of the
flags we have now, though I will let others tackle that.

llvm-svn: 45843
2008-01-10 23:08:24 +00:00
Chris Lattner f171482a66 verify that the frame index is immutable before remat'ing (still disabled)
or being side-effect free.

llvm-svn: 45816
2008-01-10 04:16:31 +00:00
Chris Lattner 9129f51f9b add a testcase
llvm-svn: 45768
2008-01-09 00:37:18 +00:00
Bill Wendling a3bdad153f Operand 1 should be a register. We don't care if it's a preg, vreg, or 0.
llvm-svn: 45699
2008-01-07 08:05:29 +00:00
Chris Lattner 03ad885039 rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.

llvm-svn: 45695
2008-01-07 07:27:27 +00:00
Chris Lattner b0d06b4381 Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
llvm-svn: 45680
2008-01-07 03:13:06 +00:00
Chris Lattner f0f438a517 remove MachineOpCode typedef.
llvm-svn: 45679
2008-01-07 02:48:55 +00:00
Chris Lattner e55e115616 Add predicates methods to TargetOperandInfo, and switch all clients
over to using them, instead of diddling Flags directly.  Change the
various flags from const variables to enums.

llvm-svn: 45677
2008-01-07 02:39:19 +00:00
Chris Lattner a98c679de0 Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.

Move a variety of predicates from TargetInstrInfo into 
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around.  Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.

Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.

llvm-svn: 45674
2008-01-07 01:56:04 +00:00
Owen Anderson 2a3be7bb6c Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Bill Wendling 5fa2c64b78 Fix comment.
llvm-svn: 45638
2008-01-05 23:30:51 +00:00
Bill Wendling be984cf10b Chris and Evan noticed that this check was compleatly fubared. I was
checking that there was a from a global instead of a load from the stub
for a global, which is the one that's safe to hoist.

Consider this program:

volatile char G[100];
int B(char *F, int N) {
  for (; N > 0; --N)
    F[N] = G[N];
}

In static mode, we shouldn't be hoisting the load from G:

$ llc -relocation-model=static -o - a.bc -march=x86 -machine-licm

LBB1_1: # bb.preheader
        leal    -1(%eax), %edx
        testl   %edx, %edx
        movl    $1, %edx
        cmovns  %eax, %edx
        xorl    %esi, %esi
LBB1_2: # bb
        movb    _G(%eax), %bl
        movb    %bl, (%ecx,%eax)

llvm-svn: 45626
2008-01-05 09:18:04 +00:00
Chris Lattner e0f0c4aa02 enable sinking and licm of loads from the argument area. I'd like to enable this
for remat, but can't due to an RA bug.

llvm-svn: 45623
2008-01-05 06:10:42 +00:00
Chris Lattner d4738ee8e1 simplify some code by using shorter accessors.
llvm-svn: 45622
2008-01-05 05:28:30 +00:00
Chris Lattner 86f4a2e4f2 revert my previous patch.
llvm-svn: 45621
2008-01-05 05:26:26 +00:00
Chris Lattner 69d7902cf1 factor some code better to avoid redundancy between
isReallySideEffectFree and isReallyTriviallyReMaterializable.  Why is a load from
a global considered side-effect-free but not rematable?

llvm-svn: 45620
2008-01-05 05:19:56 +00:00
Owen Anderson 6bb0c52628 Move some more functionality from MRegisterInfo to TargetInstrInfo.
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Bill Wendling e1f28e7871 Machine LICM will check that operands are defined outside of the loop. Also
check that register isn't 0 before going further.

llvm-svn: 45498
2008-01-02 21:10:40 +00:00
Owen Anderson eee14601b1 Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner b0fb17fd34 Fix a bug in my previous patch: refer to the impl not the pure virtual version. It's unclear why gcc would ever compile this...
llvm-svn: 45476
2008-01-01 01:05:34 +00:00
Chris Lattner 25568e4cef Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00