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43 Commits

Author SHA1 Message Date
Evan Cheng 35ff79370b Local spiller optimization: 
Turn a store folding instruction into a load folding instruction. e.g.
     xorl  %edi, %eax
     movl  %eax, -32(%ebp)
     movl  -36(%ebp), %eax
     orl   %eax, -32(%ebp)
=>
     xorl  %edi, %eax
     orl   -36(%ebp), %eax
     mov   %eax, -32(%ebp)
This enables the unfolding optimization for a subsequent instruction which will
also eliminate the newly introduced store instruction.

llvm-svn: 43192
 2007-10-19 21:23:22 +00:00
Arnold Schwaighofer 1f0da1fefb Corrected many typing errors. And removed 'nest' parameter handling 
for fastcc from X86CallingConv.td.  This means that nested functions
are not supported for calling convention 'fastcc'.

llvm-svn: 42934
 2007-10-12 21:30:57 +00:00
Arnold Schwaighofer 9ccea99165 Added tail call optimization to the x86 back end. It can be 
enabled by passing -tailcallopt to llc.  The optimization is
performed if the following conditions are satisfied:
* caller/callee are fastcc
* elf/pic is disabled OR
  elf/pic enabled + callee is in module + callee has
  visibility protected or hidden

llvm-svn: 42870
 2007-10-11 19:40:01 +00:00
Evan Cheng 1151ffde70 Commute x86 cmove instructions by swapping the operands and change the condition 
to its inverse.
Testing this as llcbeta

llvm-svn: 42661
 2007-10-05 23:13:21 +00:00
Evan Cheng aac0f8e351 Add support to convert more 64-bit instructions to 3-address instructions. 
llvm-svn: 42642
 2007-10-05 18:20:36 +00:00
Evan Cheng 97eba74a52 ADC and SBB uses EFLAGS. 
llvm-svn: 42640
 2007-10-05 17:59:57 +00:00
Evan Cheng 5fb5a1f389 Enabling new condition code modeling scheme. 
llvm-svn: 42459
 2007-09-29 00:00:36 +00:00
Evan Cheng 5a71402be6 Doh. Calls clobber EFLAGS. 
llvm-svn: 42413
 2007-09-27 19:01:55 +00:00
Evan Cheng b93de587cb Some assemblers do not recognize aliases pushfd, pushfq, popfd, and popfq. Just emit them as pushf and popf. 
llvm-svn: 42371
 2007-09-26 21:28:00 +00:00
Evan Cheng b4b352656a Typos: POPQ -> POPFQ, POPD -> POPFD. 
llvm-svn: 42348
 2007-09-26 06:38:29 +00:00
Evan Cheng 0a6f47cff9 Add pushf{d|q}, popf{d|q} to push and pop EFLAGS register. 
llvm-svn: 42335
 2007-09-26 01:29:06 +00:00
Evan Cheng e95f391ef1 Added support for new condition code modeling scheme (i.e. physical register dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after 
all the kinks are worked out.

llvm-svn: 42285
 2007-09-25 01:57:46 +00:00
Dan Gohman 96aee15d33 Use xorl instead of xorq to enter a zero into a 64-bit register. 
llvm-svn: 42027
 2007-09-17 14:55:08 +00:00
Dan Gohman 51d1929b9e Use "test reg,reg" in place of "cmp reg,0" for 64-bit operands. This was 
previously only done for 32-bit and smaller operands.

llvm-svn: 42024
 2007-09-17 14:35:24 +00:00
Dan Gohman 48ea03d169 Add patterns for SHLD64* and SHRD64*. 
llvm-svn: 41975
 2007-09-14 23:17:45 +00:00
Evan Cheng 483e1ce16e Add implicit def of EFLAGS on those instructions that may modify flags. 
llvm-svn: 41962
 2007-09-14 21:48:26 +00:00
Evan Cheng 3e18e504ae Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Dan Gohman a95cbb0007 Avoid storing and reloading zeros and other constants from stack slots 
by flagging the associated instructions as being trivially rematerializable.

llvm-svn: 41775
 2007-09-07 21:32:51 +00:00
Evan Cheng c2081fe573 Mark load instructions with isLoad = 1. 
llvm-svn: 41595
 2007-08-30 05:49:43 +00:00
Evan Cheng 9a3b2b09ad Mac OS X X86-64 low 4G address not available. 
llvm-svn: 40702
 2007-08-01 23:46:10 +00:00
Dan Gohman 54ec4bfa5f Change the x86 assembly output to use tab characters to separate the 
mnemonics from their operands instead of single spaces. This makes the
assembly output a little more consistent with various other compilers
(f.e. GCC), and slightly easier to read. Also, update the regression
tests accordingly.

llvm-svn: 40648
 2007-07-31 20:11:57 +00:00
Evan Cheng 12c6be84ff Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load ) 
llvm-svn: 40628
 2007-07-31 08:04:03 +00:00
Christopher Lamb 5fecb80efa Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource. 
llvm-svn: 40578
 2007-07-29 01:24:57 +00:00
Bill Wendling 3d88e9940a Add missing SSE builtins: 
__builtin_ia32_cvtss2si64
    __builtin_ia32_cvttss2si64
    __builtin_ia32_cvtsi642ss
    __builtin_ia32_cvtsd2si64
    __builtin_ia32_cvttsd2si64
    __builtin_ia32_cvtsi642sd

llvm-svn: 40411
 2007-07-23 03:07:27 +00:00
Evan Cheng ac1591be42 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng 94b5a80b93 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Dan Gohman c98815ba32 Define the pushq instruction for x86-64. 
llvm-svn: 37625
 2007-06-18 14:12:56 +00:00
Chris Lattner 13f4bf5c5e add support for 128-bit integer add/sub 
llvm-svn: 37154
 2007-05-17 06:35:11 +00:00
Bill Wendling c8264ca457 Have MMX registers clobbered in x86-64 too. 
llvm-svn: 36494
 2007-04-26 21:06:48 +00:00
Evan Cheng 2f4cdc78fa Some AT&T syntax assembler (e.g. Mac OS X) does not recognize the movq alias for i64 <-> XMM moves. 
llvm-svn: 32609
 2006-12-15 19:58:58 +00:00
Evan Cheng 735fcf74d8 f64 <-> i64 bit_convert using movq in 64-bit mode. 
llvm-svn: 32587
 2006-12-14 21:55:39 +00:00
Evan Cheng e50b17e97e Fix a couple of typo's. 
llvm-svn: 32585
 2006-12-14 19:46:06 +00:00
Evan Cheng dd60ca029c - Switch X86-64 JIT to large code size model. 
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.

llvm-svn: 32238
 2006-12-05 19:50:18 +00:00
Evan Cheng 62cdc3f011 - Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit 
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.

llvm-svn: 32215
 2006-12-05 04:01:03 +00:00
Evan Cheng ae1cd75af7 - Use a different wrapper node for RIP-relative GV, etc. 
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.

llvm-svn: 32046
 2006-11-30 21:55:46 +00:00
Evan Cheng 8ddbdc70b7 Fix JIT encoding bugs for shift / rotate by one ops. 
llvm-svn: 31952
 2006-11-28 01:28:00 +00:00
Evan Cheng 572dc9cb4e Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64. 
llvm-svn: 31795
 2006-11-16 23:33:25 +00:00
Chris Lattner 9ac6442db6 remove dead/redundant vars 
llvm-svn: 31435
 2006-11-03 23:48:56 +00:00
Evan Cheng 577ef7694e Add properties to ComplexPattern. 
llvm-svn: 30891
 2006-10-11 21:03:53 +00:00
Evan Cheng e71fe34d75 Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes. 
llvm-svn: 30844
 2006-10-09 20:57:25 +00:00
Evan Cheng 4259a0f654 X86ISD::CMP now produces a chain as well as a flag. Make that the chain 
operand of a conditional branch to allow load folding into CMP / TEST
instructions.

llvm-svn: 30241
 2006-09-11 02:19:56 +00:00
Evan Cheng 7348403d42 Remove TEST64mr. It's same as TEST64rm since and is commutative. 
llvm-svn: 30178
 2006-09-08 06:56:55 +00:00
Evan Cheng 11b0a5dbd4 Committing X86-64 support. 
llvm-svn: 30177
 2006-09-08 06:48:29 +00:00