73193f2475
The ARM disassembler was confused with the 16-bit tSTMIA instruction.
...
According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available.
Ignore tSTMIA for the decoder emitter and add a test case for that.
llvm-svn: 128246
2011-03-24 23:21:14 +00:00
71536de752
Move test in x86 specific area.
...
llvm-svn: 128245
2011-03-24 22:39:09 +00:00
303e3161bb
Suppress an unused variable warning in -asserts builds
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llvm-svn: 128244
2011-03-24 22:05:48 +00:00
9302df0ad9
Handle the added VBICiv*i* NEON instructions, too.
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llvm-svn: 128243
2011-03-24 22:04:39 +00:00
3a213a50fe
Testcase for llvm-gcc commit r128230.
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llvm-svn: 128242
2011-03-24 21:59:03 +00:00
02e59ad506
Plug a leak by ThumbDisassembler::getInstruction(), thanks to Benjamin Kramer!
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llvm-svn: 128241
2011-03-24 21:42:55 +00:00
6469ca0c33
T2 Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add a test case.
llvm-svn: 128240
2011-03-24 21:36:56 +00:00
dd9eb21c3f
Plug a leak in the arm disassembler and put the tests back.
...
llvm-svn: 128238
2011-03-24 21:14:28 +00:00
f170f8bff6
Add asm parsing support w/ testcases for strex/ldrex family of instructions
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llvm-svn: 128236
2011-03-24 21:04:58 +00:00
471f5aa233
Remove these two test files as they cause llvm-i686-linux-vg_leak build to fail 'test-llvm'.
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These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble.
llvm-svn: 128235
2011-03-24 20:56:23 +00:00
8bbc12824a
ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.
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Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to
the more generic ADDri/SUBri instructions, and add a test case for that.
llvm-svn: 128234
2011-03-24 20:42:48 +00:00
e01b75cb89
Keep track of directory namd and fIx regression caused by Rafael's patch r119613.
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A better approach would be to move source id handling inside MC.
llvm-svn: 128233
2011-03-24 20:30:50 +00:00
a3df87fb01
Clean up assembly statement separator support.
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The MC asm lexer wasn't honoring a non-default (anything but ';') statement
separator. Fix that, and generalize a bit to support multi-character
statement separators.
llvm-svn: 128227
2011-03-24 18:46:34 +00:00
c5207f7167
The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the
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VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case.
llvm-svn: 128226
2011-03-24 18:40:38 +00:00
1dd041083d
Add comments to the handling of opcode CPS3p to reject invalid instruction encoding,
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a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range.
llvm-svn: 128220
2011-03-24 17:04:22 +00:00
a4ec5b2c19
revert r128199 until it can be made to work with Frontend/dependency-gen.c.
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llvm-svn: 128218
2011-03-24 16:43:37 +00:00
74157ab3e5
Debug intrinsics must be skipped at the beginning and ends of blocks, lest they
...
affect the generated code.
llvm-svn: 128217
2011-03-24 16:34:59 +00:00
b03bd5983d
Fix typo in comment.
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llvm-svn: 128216
2011-03-24 16:18:19 +00:00
669ce55a42
fix description, PR9542
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llvm-svn: 128214
2011-03-24 16:13:31 +00:00
2edfe778ec
It is enough for the CallInst to have no uses to be made a tail call with a ret
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void; it doesn't need to have a void type.
llvm-svn: 128212
2011-03-24 15:54:11 +00:00
8f606d7b9b
s/UpdateDT/ModifiedDT/g
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llvm-svn: 128211
2011-03-24 15:35:25 +00:00
521eb7c11e
Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.
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FIXME: Some cleanups would be needed.
llvm-svn: 128206
2011-03-24 07:07:00 +00:00
3854bad4a1
llvm-stub.cpp: mingw-w64 tweak.
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llvm-svn: 128205
2011-03-24 07:06:45 +00:00
e8954f1ee1
Add comment to clarify what MachineConstantPoolEntry::isMachineConstantPoolEntry() means.
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llvm-svn: 128204
2011-03-24 06:28:45 +00:00
f098bf1199
Nasty bug in ARMBaseInstrInfo::produceSameValue(). The MachineConstantPoolEntry
...
entries being compared may not be ARMConstantPoolValue. Without checking
whether they are ARMConstantPoolValue first, and if the stars and moons
are aligned properly, the equality test may return true (when the first few
words of two Constants' values happen to be identical) and very bad things can
happen.
rdar://9125354
llvm-svn: 128203
2011-03-24 06:20:03 +00:00
e42162ad59
Remove all uses of PATH_MAX and MAXPATHLEN from PathV2.
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llvm-svn: 128199
2011-03-24 05:23:40 +00:00
4649f17db1
Do early taildup of ret in CodeGenPrepare for potential tail calls that have a
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void return type. This fixes PR9487.
llvm-svn: 128197
2011-03-24 04:52:10 +00:00
0e331c05ae
Use an early return instead of a long if block.
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llvm-svn: 128196
2011-03-24 04:52:07 +00:00
dd84bcce8f
When UpdateDT is set, DT is invalid, which could cause problems when trying to
...
use it later. I couldn't make a test that hits this with the current code.
llvm-svn: 128195
2011-03-24 04:52:04 +00:00
47e7175fe9
Check for TLI so that -codegenprepare can be used from opt.
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llvm-svn: 128194
2011-03-24 04:51:51 +00:00
a75d158c41
CPS3p: Let's reject impossible imod values by returning false from the DisassembleMiscFrm() function.
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Fixed rdar://problem/9179416 ARM disassembler crash: "Unknown imod operand" (fuzz testing)
Opcode=98 Name=CPS3p Format=ARM_FORMAT_MISCFRM(26)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------
Before:
cpsUnknown imod operand
UNREACHABLE executed at /Volumes/data/lldb/llvm/lib/Target/ARM/InstPrinter/../ARMBaseInfo.h:123!
After:
/Volumes/data/Radar/9179416/mc-input-arm.txt:1:1: warning: invalid instruction encoding
0x93 0x1c 0x2 0xf1
^
llvm-svn: 128192
2011-03-24 02:24:36 +00:00
0f5d52d658
Load/Store Multiple:
...
These instructions were changed to not embed the addressing mode within the MC instructions
We also need to update the corresponding assert stmt. Also add two test cases.
llvm-svn: 128191
2011-03-24 01:40:42 +00:00
1de8cc6f95
STRT and STRBT was incorrectly tagged as IndexModeNone during the refactorings (r119821).
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We now tag them as IndexModePost.
llvm-svn: 128189
2011-03-24 01:07:26 +00:00
f949d8e13d
The r128103 fix to cope with the removal of addressing modes from the MC instructions
...
were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong.
Fix the bad logic and add some sanity checking to detect bad instruction encoding;
and add a test case.
llvm-svn: 128186
2011-03-24 00:28:38 +00:00
67d3d915cc
Runtime dylib simple ARM 24-bit branch relocation support.
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llvm-svn: 128184
2011-03-23 23:35:17 +00:00
abc77347a7
Enable GlobalMerge on darwin.
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llvm-svn: 128183
2011-03-23 23:34:19 +00:00
c7ca640529
Fix comments.
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llvm-svn: 128182
2011-03-23 23:32:48 +00:00
4ab9a16569
Revert r128175.
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I'm backing this out for the second time. It was supposed to be fixed by r128164, but the mingw self-host must be defeating the fix.
llvm-svn: 128181
2011-03-23 23:11:02 +00:00
425489d397
Cmp peephole optimization isn't always safe for signed arithmetics.
...
int tries = INT_MAX;
while (tries > 0) {
tries--;
}
The check should be:
subs r4, #1
cmp r4, #0
bgt LBB0_1
The subs can set the overflow V bit when r4 is INT_MAX+1 (which loop
canonicalization apparently does in this case). cmp #0 would have cleared
it while not changing the N and Z bits. Since BGT is dependent on the V
bit, i.e. (N == V) && !Z, it is not safe to eliminate the cmp #0 .
rdar://9172742
llvm-svn: 128179
2011-03-23 22:52:04 +00:00
4c192305bf
PR9535: add support for splitting and scalarizing vector ISD::FP_ROUND.
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Also cleaning up some duplicated code while I'm here.
llvm-svn: 128176
2011-03-23 22:18:48 +00:00
4046a0de91
Reapply Eli's r127852 now that the pre-RA scheduler can spill EFLAGS.
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(target-specific branchless method for double-width relational comparisons on x86)
llvm-svn: 128175
2011-03-23 22:16:02 +00:00
c80099aa04
Split out relocation resolution into target-specific bits.
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llvm-svn: 128173
2011-03-23 22:06:06 +00:00
8543d4f8a1
The high bit of a Thumb2 ADR's offset is stored in bit 26, not bit 25.
...
This fixes 464.h264ref with the integrated assembler.
llvm-svn: 128172
2011-03-23 22:03:44 +00:00
98775c4358
Fix double-free of Module.
...
The ExecutionEngine constructor already added the module, so there's no
need to call addModule() directly. Doing so causes a double-free of the
Module at program termination.
llvm-svn: 128171
2011-03-23 21:35:02 +00:00
ab234158b8
Fix a bug introduced by my patch yesterday: BL is a 4-byte instructions like BLX, rather than a 2-byte instruction like B.
...
llvm-svn: 128169
2011-03-23 21:19:56 +00:00
13acae040c
Ensure that def-side physreg copies are scheduled above any other uses
...
so the scheduler can't create new interferences on the copies
themselves. Prior to this fix the scheduler could get stuck in a loop
creating copies.
Fixes PR9509.
llvm-svn: 128164
2011-03-23 20:42:39 +00:00
a8846e0540
whitespace
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llvm-svn: 128163
2011-03-23 20:40:18 +00:00
6a85a05130
Start of relocation resolution for the runtime dyld library.
...
llvm-svn: 128161
2011-03-23 19:52:00 +00:00
c114d89ea2
Make sure to report any errors from the runtime dyld.
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llvm-svn: 128160
2011-03-23 19:51:34 +00:00
a87d80cdca
Don't coalesce identical DBG_VALUE instructions prematurely.
...
Each of these instructions may have a RegsClobberInsn entry that can't be
ignored. Consecutive ranges are coalesced later when DwarfDebug::emitDebugLoc
merges entries.
llvm-svn: 128155
2011-03-23 18:37:30 +00:00
Johnny Chen