70f4524427
Invert and-of-or into or-of-and when doing so would allow us to clear bits of the and's mask.
...
This can result in increased opportunities for store narrowing in code generation. Update a number of
tests for this change. This fixes <rdar://problem/8285027>.
Additionally, because this inverts the order of ors and ands, some patterns for optimizing or-of-and-of-or
no longer fire in instances where they did originally. Add a simple transform which recaptures most of these
opportunities: if we have an or-of-constant-or and have failed to fold away the inner or, commute the order
of the two ors, to give the non-constant or a chance for simplification instead.
llvm-svn: 113679
2010-09-11 05:48:06 +00:00
27dddd1fd1
Rename ConvertToSetZeroFlag to something more general.
...
llvm-svn: 113670
2010-09-11 00:13:50 +00:00
d0a5f4e238
No need to recompute the SrcReg and CmpValue.
...
llvm-svn: 113666
2010-09-10 23:46:12 +00:00
041230014c
Move some of the decision logic for converting an instruction into one that sets
...
the 'zero' bit down into the back-end. There are other cases where this logic
isn't sufficient, so they should be handled separately.
llvm-svn: 113665
2010-09-10 23:34:19 +00:00
72497e5d90
Start sketching out ARM fast-isel calls.
...
llvm-svn: 113662
2010-09-10 23:18:12 +00:00
cc766a20d3
For consistency.
...
llvm-svn: 113659
2010-09-10 23:10:30 +00:00
cc1367851b
Newline at end of file.
...
llvm-svn: 113654
2010-09-10 22:46:03 +00:00
f3ecfd0e53
Fix a comment typo.
...
llvm-svn: 113653
2010-09-10 22:42:21 +00:00
1c06917f15
Split out some of the calling convention bits so that they can be
...
used for fast-isel.
llvm-svn: 113652
2010-09-10 22:42:06 +00:00
8c35fb0739
Teach InstructionSimplify to fold (A & B) & A -> A & B and (A | B) | A -> A | B.
...
Reassociate does this but it doesn't catch all cases (e.g. if the operands are i1).
llvm-svn: 113651
2010-09-10 22:39:55 +00:00
2f5f696b66
typoes
...
llvm-svn: 113647
2010-09-10 22:25:58 +00:00
aee679bf35
Modify the comparison optimizations in the peephole optimizer to update the
...
iterator when an optimization took place. This allows us to do more insane
things with the code than just remove an instruction or two.
llvm-svn: 113640
2010-09-10 21:55:43 +00:00
1f77ee5691
Add a missing case to duplicateCPV() for LSDA constants. Add a FIXME. rdar://8302157
...
llvm-svn: 113637
2010-09-10 21:38:22 +00:00
dc38d36ccb
CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.
...
llvm-svn: 113632
2010-09-10 21:14:25 +00:00
baa5d045c9
Add X86 MMX type to bitcode and Type.
...
(The Ada bindings probably need it too, but all the
obvious places to change say "do not edit this file".)
llvm-svn: 113618
2010-09-10 20:55:01 +00:00
55165fed5d
Use StringRef which performs the "early exit" when compared against a constant
...
string.
llvm-svn: 113615
2010-09-10 20:42:26 +00:00
6095d818e5
Add DEBUG message.
...
llvm-svn: 113614
2010-09-10 20:32:09 +00:00
798725b24d
Reapply r113585. The msvc machine is mercurial.
...
llvm-svn: 113610
2010-09-10 20:20:28 +00:00
77ab138f84
This transform is also performed by InstructionSimplify, remove the duplicate.
...
llvm-svn: 113608
2010-09-10 19:52:35 +00:00
a9c9aaa839
r113585 was causing clang-i686-xp-msvc9 to fail in mysterious ways that I can't
...
understand (the log file was no help).
llvm-svn: 113605
2010-09-10 19:20:47 +00:00
6a57e249df
Early exit with simple checks.
...
llvm-svn: 113603
2010-09-10 19:06:58 +00:00
e26fffc597
Auto-upgrade the magic ".llvm.eh.catch.all.value" global to
...
"llvm.eh.catch.all.value". Only the name needs to be changed.
llvm-svn: 113600
2010-09-10 18:51:56 +00:00
ed19768cec
Calculate the number of VLDM/VSTM registers by subtracting the number of
...
fixed operands from the total number of operands (including the variadic ones).
llvm-svn: 113597
2010-09-10 18:25:35 +00:00
d85c9ccdba
Lower the unrolling theshold to 150. Empirical tests indicate that this is a sweet spot in the performance per
...
code size increase curve.
llvm-svn: 113595
2010-09-10 17:57:00 +00:00
638a098f72
Mark the sse_load_f32 and sse_load_f64 load patterns as having memoperands so
...
that the memoperands are properly set after DAG building and general mucking
about.
llvm-svn: 113585
2010-09-10 10:34:22 +00:00
ac0ad0f634
Reword since this may not be a bug but intended behavior.
...
llvm-svn: 113584
2010-09-10 10:31:11 +00:00
8617234658
Fix merging base-updates for VLDM/VSTM: Before I switched these instructions
...
to use AddrMode4, there was a count of the registers stored in one of the
operands. I changed that to just count the operands but forgot to adjust for
the size of D registers. This was noticed by Evan as a performance problem
but it is a potential correctness bug as well, since it is possible that this
could merge a base update with a non-matching immediate.
llvm-svn: 113576
2010-09-10 05:15:04 +00:00
bf4070756f
Teach if-converter to be more careful with predicating instructions that would
...
take multiple cycles to decode.
For the current if-converter clients (actually only ARM), the instructions that
are predicated on false are not nops. They would still take machine cycles to
decode. Micro-coded instructions such as LDM / STM can potentially take multiple
cycles to decode. If-converter should take treat them as non-micro-coded
simple instructions.
llvm-svn: 113570
2010-09-10 01:29:16 +00:00
712bd0a604
Fix build error.
...
llvm-svn: 113566
2010-09-10 00:35:09 +00:00
860fc9370f
Update comments, reorganize some code, rename variables to be
...
more clear. No functional change.
llvm-svn: 113565
2010-09-10 00:34:35 +00:00
22fd29a94a
64-bit fp loads can come straight out of the constant pool, not as
...
bad as I'd thought.
llvm-svn: 113561
2010-09-09 23:50:00 +00:00
6dbbab6895
Discard metadata produced by LLVM 2.7. The value enumeration it used
...
is different from what the code now uses in a two ways: NamedMDNodes
were considered Values and included in the numbering, and the
function-local metadata counter wasn't reset between functions.
The later problem breaks lazy deserialization, so instead of trying
to emulate the old numbering, just drop the old metadata. The only
in-tree use case is debug info with LTO, where the QOI loss is
considered acceptable.
llvm-svn: 113557
2010-09-09 23:12:39 +00:00
e5444a88cd
llvm-mc: Don't crash when using -n and we see a directive before the initial section.
...
- This is annoying, because we have to scatter this check everywhere that could emit real data, but I see no better solution.
llvm-svn: 113552
2010-09-09 22:42:59 +00:00
43325c4a68
llvm-mc: Make sure we exit != 0 if any errors are encountered.
...
llvm-svn: 113551
2010-09-09 22:42:56 +00:00
4bd7047324
SIToFP and FPToSI conversions work only on fp-reg to fp-reg. Move
...
some data around and implement a couple of move routines to do this.
llvm-svn: 113546
2010-09-09 21:44:45 +00:00
f942e96ed5
MDNodes are not Constants.
...
llvm-svn: 113539
2010-09-09 20:54:24 +00:00
0a54da2fce
Print invalid metadata references as <badref>, for consistency with
...
regular value references.
llvm-svn: 113538
2010-09-09 20:53:58 +00:00
2cbe0fd956
New "move to fp reg" routine. Use it.
...
llvm-svn: 113537
2010-09-09 20:49:25 +00:00
82b05d7206
"Strike that, reverse it." -- Mr. Wonka.
...
Truncate when truncating, extend when extending.
llvm-svn: 113536
2010-09-09 20:36:19 +00:00
04cf3fd761
What the loop unroller cares about, rather than just not unrolling loops with calls, is
...
not unrolling loops that contain calls that would be better off getting inlined. This mostly
comes up when an interleaved devirtualization pass has devirtualized a call which the inliner
will inline on a future pass. Thus, rather than blocking all loops containing calls, add
a metric for "inline candidate calls" and block loops containing those instead.
llvm-svn: 113535
2010-09-09 20:32:23 +00:00
5903c0be2a
Add FPTrunc, fix some bugs where I forgot to update the value map.
...
llvm-svn: 113533
2010-09-09 20:26:31 +00:00
6270515918
Revert r113439, which relaxed the requirement that loops containing calls cannot be unrolled. After some discussion,
...
there seems to be a better way to achieve the same effect.
llvm-svn: 113528
2010-09-09 20:02:23 +00:00
11ab204fdc
r113526 introduced an unintended change to the loop unrolling threshold. Revert it.
...
llvm-svn: 113527
2010-09-09 19:11:57 +00:00
b61b1647e2
Fix typo in code to cap the loop code size reduction calculation.
...
llvm-svn: 113526
2010-09-09 19:08:59 +00:00
62ea1b718c
Use code-size reduction metrics to estimate the amount of savings we'll get when we unroll a loop.
...
Next step is to recalculate the threshold values given this new heuristic.
llvm-svn: 113525
2010-09-09 19:07:31 +00:00
6e3eeba4d9
Basic FP->Int, Int->FP conversions.
...
llvm-svn: 113523
2010-09-09 18:54:59 +00:00
e8501a468c
Add one more pattern to fallback movddup
...
llvm-svn: 113522
2010-09-09 18:48:34 +00:00
1c5be00ec7
Extend the getDependence query with support for PHI translation.
...
llvm-svn: 113521
2010-09-09 18:37:31 +00:00
367a5df8cf
For each instruction itinerary class, specify the number of micro-ops each
...
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
6c3c349b2b
MCELF: Write relocation fragments in the right endian.
...
- This code is gross, but does the job for now.
llvm-svn: 113509
2010-09-09 18:01:29 +00:00
3b727f55aa
Make ELF OS ABI dependent on the OS from target triple.
...
llvm-svn: 113508
2010-09-09 17:57:50 +00:00
0ec303b97b
Move remaining MMX instructions from SSE to MMX.
...
llvm-svn: 113501
2010-09-09 17:13:07 +00:00
a08318acb2
Refactor code-size reduction estimation methods out of InlineCostAnalyzer and into CodeMetrics. They
...
don't use any InlineCostAnalyzer state, and are useful for other clients who don't necessarily want to use
all of InlineCostAnalyzer's logic, some of which is fairly inlining-specific.
No intended functionality change.
llvm-svn: 113499
2010-09-09 16:56:42 +00:00
a90e25cc64
MC: Give a (lame) hard error if a .org directive would create an unreasonably
...
large object file (> 1GB).
llvm-svn: 113494
2010-09-09 16:23:33 +00:00
19e11f1db7
lib/System/Host.cpp: 7bit-ize. Eliminate "TM" and "(R)" in comments.
...
llvm-svn: 113486
2010-09-09 13:30:48 +00:00
01cda2d35a
Silence compiler warning.
...
llvm-svn: 113478
2010-09-09 07:30:15 +00:00
4adbaf1843
Fix NEON VLD pseudo instruction itineraries that were incorrectly copied from
...
the VST pseudos. The VLD/VST scheduling still needs work (see pr6722), but
at least we shouldn't confuse the loads with the stores.
llvm-svn: 113473
2010-09-09 05:40:26 +00:00
2ff757d422
Nuke whitespace and fix some indenting.
...
llvm-svn: 113463
2010-09-09 01:06:51 +00:00
5f4a6f295c
Move most MMX instructions (defined as anything that
...
uses MMX, even if it also uses other things) from InstrSSE
into InstrMMX. No (intended) functional change.
llvm-svn: 113462
2010-09-09 01:02:39 +00:00
bd3d121641
Handle 64-bit floating point binops as well.
...
llvm-svn: 113461
2010-09-09 01:02:03 +00:00
24dc27f73a
Basic 32-bit FP operations.
...
llvm-svn: 113459
2010-09-09 00:53:57 +00:00
84971c850a
For double-spaced VLD3/VLD4 instructions, copy the explicit super-register use
...
operand from the pseudo instruction to the new instruction as an implicit use.
This will preserve any other flags (e.g., kill) on the operand.
llvm-svn: 113456
2010-09-09 00:38:32 +00:00
f14b9bf98d
Handle float->double extension.
...
llvm-svn: 113455
2010-09-09 00:26:48 +00:00
3cf63f1edd
Rewrite TargetMaterializeConstant splitting it out into two functions
...
for integer and fp constants. Implement todo to use vfp3 instructions
to materialize easy constants if we can.
llvm-svn: 113453
2010-09-09 00:19:41 +00:00
4ccd5ce6ea
Simplify copying over operands from pseudo NEON load/store instructions.
...
For VLD3/VLD4 with double-spaced registers, add the implicit use of the
super register for both the instruction loading the even registers and the
instruction loading the odd registers.
llvm-svn: 113452
2010-09-09 00:15:32 +00:00
359f8ba337
Clean up a comment.
...
llvm-svn: 113442
2010-09-08 23:39:54 +00:00
c3e9c404aa
Very basic compare support.
...
llvm-svn: 113440
2010-09-08 23:13:45 +00:00
8084dbaf8e
Relax the "don't unroll loops containing calls" rule. Instead, when a loop contains a call, lower the
...
unrolling threshold to the optimize-for-size threshold. Basically, for loops containing calls, unrolling
can still be profitable as long as the loop is REALLY small.
llvm-svn: 113439
2010-09-08 23:10:07 +00:00
5838af54bf
Delete dead code.
...
llvm-svn: 113436
2010-09-08 22:58:35 +00:00
722cd122dc
Fix LDM_RET schedule itinery.
...
llvm-svn: 113435
2010-09-08 22:57:08 +00:00
28a9c2f89a
fix rdar://8407548, I missed the commuted form of xchg/test without a suffix.
...
llvm-svn: 113427
2010-09-08 22:27:05 +00:00
d7aba234c2
fix wonky formatting.
...
llvm-svn: 113426
2010-09-08 22:22:10 +00:00
3fe002dfb5
Generalize instcombine's support for combining multiple bit checks into a single test. Patch by Dirk Steinke!
...
llvm-svn: 113423
2010-09-08 22:16:17 +00:00
8ead237758
fix bugs in push/pop segment support, rdar://8407242
...
llvm-svn: 113422
2010-09-08 22:13:08 +00:00
0d2e6ad504
Add intrinsic-based patterns for MMX PINSRW and PEXTRW.
...
llvm-svn: 113420
2010-09-08 22:08:40 +00:00
6489df7c8c
Make the loads/stores match the type we really want to store.
...
llvm-svn: 113417
2010-09-08 21:49:50 +00:00
e54dba94f9
Check in forgotten file. Should fix build.
...
llvm-svn: 113409
2010-09-08 21:09:48 +00:00
4dae01781f
Slight cleanup, use only one form of MMXI_binop_rm_int.
...
llvm-svn: 113406
2010-09-08 20:54:00 +00:00
504d23bd05
Re-enable usage of the ARM base pointer. r113394 fixed the known failures.
...
Re-running some nightly testers w/ it enabled to verify.
llvm-svn: 113399
2010-09-08 20:12:02 +00:00
21c9471706
Fix errant fall-throughs causing the base pointer to be used when the frame
...
pointer was intended. rdar://8401980
llvm-svn: 113394
2010-09-08 19:55:28 +00:00
d79bb127dd
Add intrinsic forms of mmx<->sse conversions. Notes:
...
Omission of memory form of PI2PD is intentional; this
does not use an MMX register and does not put the chip
into MMX mode (PI2PS, oddly enough, does).
Operands of PI2PS follow the gcc builtin, not Intel.
llvm-svn: 113388
2010-09-08 19:15:38 +00:00
f5dd1929a2
Rewrite TargetMaterializeConstant.
...
llvm-svn: 113387
2010-09-08 18:56:34 +00:00
79e838b0a8
Remove dead code.
...
llvm-svn: 113386
2010-09-08 18:50:24 +00:00
99a9f4661a
Minor change. Fix comments and remove unused and redundant code
...
llvm-svn: 113378
2010-09-08 18:12:31 +00:00
2ef1a589c5
ELF_STB_Local is 0 so setting and checking it must be done specially
...
llvm-svn: 113375
2010-09-08 18:08:40 +00:00
8e89e41faf
Clarify the ownership model of LLVMContext and Module. Namely, contexts own
...
modules are instantiated in them. If the context is deleted, all of its owned
modules are also deleted.
llvm-svn: 113374
2010-09-08 18:03:32 +00:00
f7fee1c185
x86 vector shuffle lowering now relies only on target specific
...
nodes to emit shuffles and don't do isel mask matching anymore.
- Add the selection of the remaining shuffle opcode (movddup)
- Introduce two new functions to "recognize" where we may get
potential folds and add several comments to them explaining why
they are not yet in the desidered shape.
- Add more patterns to fallback the case where we select
a specific shuffle opcode as if it could fold a load, but it
can't, so remap to a valid instruction.
- Add a couple of FIXMEs to address in the following days once
there's a good solution to the current folding problem.
llvm-svn: 113369
2010-09-08 17:43:25 +00:00
7dfca6fb51
Be more careful about when to do dynamic stack realignment. Since we have an
...
option to disable base pointer usage, pay attention to it when deciding
if we can realign (if no base pointer and VLAs, we can't).
llvm-svn: 113366
2010-09-08 17:22:12 +00:00
53aa5e31e1
Add missing assert
...
llvm-svn: 113365
2010-09-08 17:05:45 +00:00
6c27de28b5
Unresolved weak symbols have value equal zero.
...
llvm-svn: 113358
2010-09-08 14:29:45 +00:00
e542972828
Fix CellSPU vector shuffles, again.
...
Some cases of lowering to rotate were miscompiled.
llvm-svn: 113355
2010-09-08 11:53:38 +00:00
2907d2e419
add support for the commuted form of the test instruction, rdar://8018260.
...
llvm-svn: 113352
2010-09-08 05:51:12 +00:00
a9ca7837e4
implement proper support for sysret{,l,q}, rdar://8403907
...
llvm-svn: 113350
2010-09-08 05:45:34 +00:00
063363fa80
implement the iret suite of instructions properly,
...
fixing rdar://8403974
llvm-svn: 113349
2010-09-08 05:38:31 +00:00
086a83afb1
add support for instruction prefixes on the same line as the instruction,
...
implementing rdar://8033482 and PR7254.
llvm-svn: 113348
2010-09-08 05:17:37 +00:00
91689c1d0f
change the MC "ParseInstruction" interface to make it the
...
implementation's job to check for and lex the EndOfStatement
marker.
llvm-svn: 113347
2010-09-08 05:10:46 +00:00
8caea68a4f
gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.
...
Add this to the mc assembler, fixing PR8061
llvm-svn: 113346
2010-09-08 04:53:27 +00:00
7a23aa081a
ARM/Disassembler: Fix definitions incompatible(unsigned and uint32_t) to Cygwin-1.5, following up to r113255.
...
llvm-svn: 113345
2010-09-08 04:48:17 +00:00
4703cb4a96
fix the encoding of the "jump on *cx" family of instructions,
...
rdar://8061602
llvm-svn: 113343
2010-09-08 04:30:51 +00:00
535d3b4e09
remove trailing whitespace
...
llvm-svn: 113338
2010-09-08 03:54:02 +00:00
Owen Anderson