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78348 Commits

Author SHA1 Message Date
Hal Finkel 72a26e8b8d don't include CR bit subregs in callee-saved list 
llvm-svn: 145818
 2011-12-05 17:55:12 +00:00
Hal Finkel e18c72689c remove wasted space for extra bit copies of CR2 subregs 
llvm-svn: 145817
 2011-12-05 17:55:06 +00:00
Hal Finkel b544019a60 add register pressure for CR regs 
llvm-svn: 145816
 2011-12-05 17:54:17 +00:00
Benjamin Kramer 13231037f0 Add a little heuristic to Value::isUsedInBasicBlock to speed it up for small basic blocks. 
- Calling getUser in a loop is much more expensive than iterating over a few instructions.
- Use it instead of the open-coded loop in AddrModeMatcher.
- 5% speedup on ARMDisassembler.cpp Release builds.

llvm-svn: 145810
 2011-12-05 17:23:27 +00:00
NAKAMURA Takumi e6efe405de test/CodeGen/X86/pointer-vector.ll: Add explicit -mtriple=i686-linux. 
llvm-svn: 145805
 2011-12-05 07:54:57 +00:00
Craig Topper 51bec1a37a Remove some leftover remnants that once tried to create 64-bit MMX PALIGNR instructions. 
llvm-svn: 145804
 2011-12-05 07:27:14 +00:00
Craig Topper 6a55b1dd9f Clean up and optimizations to the X86 shuffle lowering code. No functional change. 
llvm-svn: 145803
 2011-12-05 06:56:46 +00:00
Nadav Rotem 3924cb0267 Add support for vectors of pointers. 
llvm-svn: 145801
 2011-12-05 06:29:09 +00:00
Jakub Staszak 5fd147f97e Fix table of contents. 
llvm-svn: 145793
 2011-12-04 20:44:25 +00:00
Jakub Staszak 5fef792d8c Add 'llvm.expect' intrinsic description. 
llvm-svn: 145792
 2011-12-04 18:29:26 +00:00
Eric Christopher 8dda5d0f06 Add inline subprogram names to the name lookup table since they may 
not get there any other way.

llvm-svn: 145789
 2011-12-04 06:02:38 +00:00
Bob Wilson 80381f6cbf Fix 80-column issues. 
llvm-svn: 145783
 2011-12-04 00:52:23 +00:00
Anton Korobeynikov 965e0c6de2 Emit the ctors in the proper order on ARM/EABI. 
Maybe some targets should use this as well.

Patch by Evgeniy Stepanov!

llvm-svn: 145781
 2011-12-03 23:49:37 +00:00
Venkatraman Govindaraju 6dae604f50 Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 
AnalyzeBranch doesn't change the successor, just the order.

llvm-svn: 145779
 2011-12-03 21:24:48 +00:00
Benjamin Kramer 71ba18c1e0 Simplify code. No functionality change. 
-3% on ARMDissasembler.cpp.

llvm-svn: 145773
 2011-12-03 16:18:22 +00:00
Benjamin Kramer bbf3c60786 Clear the new cache. 
llvm-svn: 145771
 2011-12-03 15:19:55 +00:00
Benjamin Kramer 3664708378 Add a "seen blocks" cache to LVI to avoid a linear scan over the whole cache just to remove no blocks from the maps. 
-15% on ARMDisassembler.cpp (Release build).  It's not that great to add another
layer of caching to the caching-heavy LVI but I don't see a better way.

llvm-svn: 145770
 2011-12-03 15:16:45 +00:00
Sanjoy Das 006e43bcc0 Check for stack space more intelligently. 
libgcc sets the stack limit field in TCB to 256 bytes above the actual
allocated stack limit.  This means if the function's stack frame needs
less than 256 bytes, we can just compare the stack pointer with the
stack limit.  This should result in lesser calls to __morestack.

llvm-svn: 145766
 2011-12-03 09:32:07 +00:00
Sanjoy Das 165ca1d4ba Fix a bug in the x86-32 code generated for segmented stacks. 
Currently LLVM pads the call to __morestack with a add and sub of 8
bytes to esp.  This isn't correct since __morestack expects the call
to be followed directly by a ret.

This commit also adjusts the relevant test-case.

llvm-svn: 145765
 2011-12-03 09:21:07 +00:00
Nick Lewycky 8fd1254a0a Creating multiple JITs on X86 in multiple threads causes multiple writes (of 
the same value) to this variable. This code could be refactored, but it doesn't
matter since the old JIT is going away. Add tsan annotations to ignore the
race.

llvm-svn: 145745
 2011-12-03 02:45:50 +00:00
Chad Rosier ec3b77e00d [arm-fast-isel] Unaligned stores of floats require special care. 
rdar://10510150

llvm-svn: 145742
 2011-12-03 02:21:57 +00:00
Pete Cooper e03fe83d98 Fixed deadstoreelimination bug where negative indices were incorrectly causing the optimisation to occur 
Turns out long long + unsigned long long is unsigned.  Doh!

Fixes http://llvm.org/bugs/show_bug.cgi?id=11455

llvm-svn: 145731
 2011-12-03 00:04:30 +00:00
Chad Rosier 0155a63513 Add support for constant folding the pow intrinsic. 
rdar://10514247

llvm-svn: 145730
 2011-12-03 00:00:03 +00:00
Jim Grosbach 9dff9f4c41 ARM NEON VEXT aliases for data type suffices. 
llvm-svn: 145726
 2011-12-02 23:34:39 +00:00
Jim Grosbach 2635f54cb6 ARM VEXT tighten up operand classes a bit. 
llvm-svn: 145722
 2011-12-02 22:57:57 +00:00
Jim Grosbach eb53822f5a ARM VST1 single lane assembly parsing. 
llvm-svn: 145718
 2011-12-02 22:34:51 +00:00
Akira Hatanaka 430f917fbe Test cases for 64-bit multiplication and division. 
llvm-svn: 145717
 2011-12-02 22:31:36 +00:00
Akira Hatanaka bbc5555bee Fix test cases to use FileCheck. 
llvm-svn: 145716
 2011-12-02 22:28:09 +00:00
Nick Lewycky 50f02cb21b Move global variables in TargetMachine into new TargetOptions class. As an API 
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.

One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.

llvm-svn: 145714
 2011-12-02 22:16:29 +00:00
Jim Grosbach 7276397f41 ARM tests for VLD1 single lane w/ writeback. 
llvm-svn: 145713
 2011-12-02 22:03:52 +00:00
Jim Grosbach dda976b804 ARM VLD1 single lane assembly parsing. 
llvm-svn: 145712
 2011-12-02 22:01:52 +00:00
Jim Grosbach 81c9003695 ARM encoder method needs the physical register number, not the enum. 
llvm-svn: 145711
 2011-12-02 22:01:25 +00:00
Dylan Noblesmith dbf20b8aaa TargetMachine: document unnamed bool argument 
Its meaning was slightly mysterious without looking at
subclasses.

llvm-svn: 145705
 2011-12-02 20:53:57 +00:00
Dylan Noblesmith f6f9f1dd4a unittests: add ErrorStr to ExecutionEngine test 
Makes failures more self-explanatory.

llvm-svn: 145704
 2011-12-02 20:53:53 +00:00
Chad Rosier 9fd0e55e91 [arm-fast-isel] After promoting a function parameter be sure to update the 
argument value type.  Otherwise, the sign/zero-extend has no effect on arguments
passed via the stack (i.e., undefined high-order bits).
rdar://10515467

llvm-svn: 145701
 2011-12-02 20:25:18 +00:00
Hal Finkel d87f7af1f3 specify cpu for test to fix failure on some darwin systems with a g4+ cpu 
llvm-svn: 145699
 2011-12-02 19:38:17 +00:00
Jim Grosbach e7dcbc8691 Clean up aliases for ARM VLD1 single-lane assembly parsing a bit. 
Add the 16-bit lane variants while I'm at it.

llvm-svn: 145693
 2011-12-02 18:52:30 +00:00
Benjamin Kramer 4d2b871cda Fix quadratic behavior in InlineFunction by fetching the personality function of the callee once and not for every invoke in the caller. 
The callee is usually smaller than the caller, too. This reduces the compile
time of ARMDisassembler.cpp by 32% (Release build). It still takes ages to
compile though.

llvm-svn: 145690
 2011-12-02 18:37:31 +00:00
Jim Grosbach bccc4c17f3 Check for error after InstantiateMultclassDef. 
llvm-svn: 145689
 2011-12-02 18:33:03 +00:00
Jan Sjödin 1280eb1d06 Add XOP feature flag. 
llvm-svn: 145682
 2011-12-02 15:14:37 +00:00
Craig Topper b67440367f Reduce duplicate code in isHorizontalBinOp and add some asserts to protect assumptions 
llvm-svn: 145681
 2011-12-02 08:18:41 +00:00
Craig Topper abeb79eee3 Add instruction selection support for horizontal add/sub of 256-bit floating point vectors. Also add the test case for 256-bit integer vectors. 
llvm-svn: 145680
 2011-12-02 07:16:01 +00:00
Hal Finkel f9ce7b60ef remove unneeded FIXME comment 
llvm-svn: 145679
 2011-12-02 04:58:17 +00:00
Hal Finkel 9286705955 adjust the instruction ordering in some PPC tests: changes due to postRA haz. rec. 
llvm-svn: 145678
 2011-12-02 04:58:12 +00:00
Hal Finkel 4201820275 make sure ScheduleDAGInstrs::EmitSchedule does not crash when the first instruction in Sequence is a Noop 
llvm-svn: 145677
 2011-12-02 04:58:07 +00:00
Hal Finkel 58ca360081 update PPC 940 hazard rec. to function in postRA mode 
llvm-svn: 145676
 2011-12-02 04:58:02 +00:00
Chad Rosier 43a33066b4 Fix a few more places where TargetData/TargetLibraryInfo is not being passed. 
Add FIXMEs to places that are non-trivial to fix.

llvm-svn: 145661
 2011-12-02 01:26:24 +00:00
Jim Grosbach 04945c42c6 ARM start parsing VLD1 single lane instructions. 
The alias pseudos need cleaned up for size suffix handling, but this gets
the basics working. Will be cleaning up and adding more.

llvm-svn: 145655
 2011-12-02 00:35:16 +00:00
Chad Rosier 576c0f8e54 Abuse of mass replace isn't warranted even when the build is failing. Thanks 
for the suggestion, Eric.

llvm-svn: 145643
 2011-12-01 23:16:03 +00:00
Chad Rosier 54a506dcb1 Fix build by not assuming TLI is guaranteed. Will have to track down cases where 
TLI isn't being passed to ensure we don't miss opportunities to fold calls.

llvm-svn: 145641
 2011-12-01 22:38:31 +00:00