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68 Commits

Author SHA1 Message Date
Krzysztof Parzyszek d0d42f0ec8 [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructions 
Patch by Colin LeMahieu.

llvm-svn: 293933
 2017-02-02 20:35:12 +00:00
Krzysztof Parzyszek e17b0bfb24 [Hexagon] Fix relocation kind for extended predicated calls 
Patch by Sid Manning.

llvm-svn: 293931
 2017-02-02 20:21:56 +00:00
Krzysztof Parzyszek 73e0ad8220 [Hexagon] Fix disassembler crash after r279255 
When p0 was added as an explicit operand to the duplex subinstructions,
the disassembler was not updated to reflect this.

llvm-svn: 281104
 2016-09-09 21:45:00 +00:00
Daniel Sanders 8e3c74210f Remove redundant -mattr options from llvm-objdump commands. 
The -mattr options in these four tests have no effect on the output of
llvm-objdump. In the case of the two Mips tests, removing the -mattr option
left duplicate RUN lines so the duplicates have been removed.

llvm-svn: 272906
 2016-06-16 15:47:19 +00:00
Krzysztof Parzyszek a053101c95 [Hexagon] Use pipe instead of temporary files in tests 
llvm-svn: 270217
 2016-05-20 14:01:34 +00:00
Krzysztof Parzyszek 7c7bb538cb [Hexagon] Treat all conditional branches as predicted (not-taken by default) 
llvm-svn: 268946
 2016-05-09 18:22:07 +00:00
Krzysztof Parzyszek f7a4bd4068 [Hexagon] Add aliases for vector loads/stores with no explicit offset 
The mem(r0) instructions are treated as mem(r0+#0).

llvm-svn: 268661
 2016-05-05 18:38:35 +00:00
Krzysztof Parzyszek e5fcce2d2b [Hexagon] Add instruction aliases for vector unsigned compare-equal 
Unsigned compare-equal instructions are mapped to signed compare-equal.

llvm-svn: 267925
 2016-04-28 19:49:18 +00:00
Krzysztof Parzyszek 0e7d2d339d [Hexagon] Define certain aliases for vector instructions 
Specifically:
  Vd = #0   -> Vd = vxor(Vd, Vd)
  Vdd = #0  -> Vdd.w = vsub(Vdd.w, Vdd.w)
  Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L)

llvm-svn: 267901
 2016-04-28 16:43:16 +00:00
Krzysztof Parzyszek e737b86f8c [Hexagon] Handle double-vector registers as new-value producers 
Patch by Colin LeMahieu.

llvm-svn: 267897
 2016-04-28 15:54:48 +00:00
Colin LeMahieu a3782da3e3 [Hexagon] Merging nops in to previous packet rather than always creating a new one. 
llvm-svn: 267798
 2016-04-27 21:37:44 +00:00
Krzysztof Parzyszek a4602b5be1 [Hexagon] Use llvm-mc instead of llc in an MC testcase 
Remember to svn add the new file.

llvm-svn: 267435
 2016-04-25 18:09:36 +00:00
Krzysztof Parzyszek 4ea9bd72df [Hexagon] Use llvm-mc instead of llc in an MC testcase 
llvm-svn: 267434
 2016-04-25 18:08:33 +00:00
Krzysztof Parzyszek e6ee481bdf [Hexagon] Correctly set "Flags" in ELF header 
llvm-svn: 267397
 2016-04-25 12:49:47 +00:00
Krzysztof Parzyszek e2c6405708 [Hexagon] Add definitions for trap/pause instructions 
Also add tests for other instructions from HexagonSystemInst.td.

llvm-svn: 267162
 2016-04-22 16:25:00 +00:00
Krzysztof Parzyszek adf02ae540 [Hexagon] Properly recognize register alt names 
llvm-svn: 267038
 2016-04-21 19:49:53 +00:00
Krzysztof Parzyszek 5626703837 [Hexagon] Fix handling of lcomm directive 
Patch by Colin LeMahieu.

llvm-svn: 266882
 2016-04-20 15:54:13 +00:00
Colin LeMahieu efe3732883 Revert r265817 
lld tests need to be addressed.

llvm-svn: 265822
 2016-04-08 18:15:37 +00:00
Colin LeMahieu 4a1975ba8e [llvm-objdump] Printing hex instead of dec by default 
Differential Revision: http://reviews.llvm.org/D18770

llvm-svn: 265817
 2016-04-08 17:55:03 +00:00
Krzysztof Parzyszek b14f4fd0de [Hexagon] Add handling fixups and instruction relaxation 
llvm-svn: 263981
 2016-03-21 20:27:17 +00:00
Krzysztof Parzyszek c6f1e1a709 [Hexagon] Properly encode registers in duplex instructions 
llvm-svn: 263980
 2016-03-21 20:13:33 +00:00
Colin LeMahieu ab9eca4d9f [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range. 
llvm-svn: 262258
 2016-02-29 21:21:56 +00:00
Colin LeMahieu ecef1d9cbc [Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding. 
The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.

Another way is to put a .word32 and mix code and data within a function.  The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.

This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits.  Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.

llvm-svn: 261006
 2016-02-16 20:38:17 +00:00
Hemant Kulkarni d8a985ec7c [llvm-readobj] Option to emit readelf like output 
New option --elf-output-style=LLVM or GNU
Enables -file-headers in readelf style when elf-output-style=GNU

Differential revision: http://reviews.llvm.org/D14128

llvm-svn: 260430
 2016-02-10 20:40:55 +00:00
Hemant Kulkarni f46c92fe52 Revert "[llvm-readobj] Option to emit readelf like output" 
This reverts commit a58765909660a7195b32e0cc8c7476168b913750.

llvm-svn: 260397
 2016-02-10 18:21:01 +00:00
Hemant Kulkarni 4f2ca0d268 [llvm-readobj] Option to emit readelf like output 
New option --elf-output-style=LLVM or GNU
Enables -file-headers in readelf style when elf-output-style=GNU

Differential revision: http://reviews.llvm.org/D14128

llvm-svn: 260391
 2016-02-10 17:51:28 +00:00
Colin LeMahieu 1c79d9be6e [Hexagon] Fixing relocation generation and adding tests. 
llvm-svn: 260259
 2016-02-09 19:18:02 +00:00
Dimitry Andric 227b928abc Fix several accidental DOS line endings in source files 
Summary:
There are a number of files in the tree which have been accidentally checked in with DOS line endings.  Convert these to native line endings.

There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.

Reviewers: joerg, aaron.ballman

Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15848

llvm-svn: 256707
 2016-01-03 17:22:03 +00:00
Krzysztof Parzyszek 21dc8bdd9e [Hexagon] Add PIC support 
llvm-svn: 256025
 2015-12-18 20:19:30 +00:00
Colin LeMahieu 15ca65c253 [Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings. 
llvm-svn: 254652
 2015-12-03 21:44:28 +00:00
Colin LeMahieu fa5558307b [Hexagon] NFC. Adding a number of packet correctness tests. 
llvm-svn: 253000
 2015-11-13 01:46:06 +00:00
Colin LeMahieu 8bb168b160 [Hexagon] Adding relaxation functionality to backend and test. 
llvm-svn: 252989
 2015-11-13 01:12:25 +00:00
Colin LeMahieu 7a92c6ecbb [Hexagon] Adding checks for values out of operand range and correct new-value producer usage. 
llvm-svn: 252969
 2015-11-12 23:28:01 +00:00
Colin LeMahieu a1fa71ead9 [Hexagon] Adding test to make sure labels and register pairs are correctly parsed. 
llvm-svn: 252968
 2015-11-12 22:54:14 +00:00
Colin LeMahieu 3c7ecf9af1 [Hexagon] Adding instruction aliases and tests. 
llvm-svn: 252579
 2015-11-10 01:58:26 +00:00
Colin LeMahieu 13cc3ab785 [Hexagon] Fixing compound register printing and reenabling more tests. 
llvm-svn: 252574
 2015-11-10 00:51:56 +00:00
Colin LeMahieu b7a5f9fc29 [Hexagon] Fixing store instructions and reenabling a few more tests. 
llvm-svn: 252561
 2015-11-10 00:22:00 +00:00
Colin LeMahieu 8ab7e8e1b5 [Hexagon] Fixing load instruction parsing and reenabling tests. 
llvm-svn: 252555
 2015-11-10 00:02:27 +00:00
Colin LeMahieu 7cd0892729 [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission. 
llvm-svn: 252443
 2015-11-09 04:07:48 +00:00
Krzysztof Parzyszek a7c5f0409c [Hexagon] Split double registers 
llvm-svn: 250549
 2015-10-16 20:38:54 +00:00
Colin LeMahieu be8c453d58 [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing. 
llvm-svn: 239161
 2015-06-05 16:00:11 +00:00
Colin LeMahieu 68d967d92e [Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch. 
llvm-svn: 238556
 2015-05-29 14:44:13 +00:00
Krzysztof Parzyszek c05dff1792 Expand MUX instructions early on Hexagon 
This time with all files included.

llvm-svn: 233696
 2015-03-31 13:35:12 +00:00
Krzysztof Parzyszek 8c4fd2bdeb Revert 233694. Weak SVN-fu. 
llvm-svn: 233695
 2015-03-31 13:32:32 +00:00
Krzysztof Parzyszek 261d62c862 Expand MUX instructions early on Hexagon 
llvm-svn: 233694
 2015-03-31 13:29:17 +00:00
Colin LeMahieu 30dcb232b0 [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. 
llvm-svn: 223800
 2014-12-09 18:16:49 +00:00
Colin LeMahieu 6e0f9f8d61 [Hexagon] Adding cmp* immediate form instructions. 
llvm-svn: 222849
 2014-11-26 19:43:12 +00:00
Colin LeMahieu 31abe33726 [Hexagon] Adding and64, or64, and xor64 instructions. 
llvm-svn: 222846
 2014-11-26 18:55:59 +00:00
Colin LeMahieu b3d08bb44b [Hexagon] Adding add64 and sub64 instructions. 
llvm-svn: 222795
 2014-11-25 22:15:44 +00:00
Colin LeMahieu 6f6c4ff1fc Reverting 222792 
llvm-svn: 222793
 2014-11-25 21:39:57 +00:00