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3 Commits

Author SHA1 Message Date
Daniel Sanders 869bdad93a [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v 
llvm-svn: 188767
 2013-08-20 08:38:21 +00:00
Jack Carter babdcc8c2c [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) 
Includes:
add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd],
bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti,
c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su],
dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve,
ldi

Patch by Daniel Sanders

llvm-svn: 188457
 2013-08-15 12:24:57 +00:00
Jack Carter 3a2c2d42b8 [Mips][msa] Added initial MSA support. 
* msa SubtargetFeature
* registers
* ld.[bhwd], and st.[bhwd] instructions

Does not correctly prohibit use of both 32-bit FPU registers and MSA together.

Patch by Daniel Sanders

llvm-svn: 188313
 2013-08-13 20:54:07 +00:00