maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
156,315 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

140 Commits

Author SHA1 Message Date
Akira Hatanaka 8dd951bc9f [mips] Remove predicates that were incorrectly or unnecessarily added. 
llvm-svn: 188845
 2013-08-20 23:21:55 +00:00
Akira Hatanaka 6781fc1648 [mips] Resolve register classes dynamically using ptr_rc to reduce the number of 
load/store instructions defined. Previously, we were defining load/store
instructions for each pointer size (32 and 64-bit), but now we need just one
definition.

llvm-svn: 188830
 2013-08-20 21:08:22 +00:00
Akira Hatanaka 8002a3f6d8 [mips] Rename HIRegs and LORegs. 
llvm-svn: 188341
 2013-08-14 00:47:08 +00:00
Akira Hatanaka 00fcf2e169 [mips] Rename accumulator register classes and FP register operands. 
llvm-svn: 188020
 2013-08-08 21:54:26 +00:00
Akira Hatanaka 85ccf23d7d [mips] Delete register class HWRegs64. 
No functionality change.

llvm-svn: 188016
 2013-08-08 21:37:32 +00:00
Akira Hatanaka 13e6ccf341 [mips] Rename register classes CPURegs and CPU64Regs. 
llvm-svn: 187832
 2013-08-06 23:08:38 +00:00
Akira Hatanaka c7e3998e45 [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates of 
instructions defined in MipsInstrInfo.td as codegen-only instructions.

llvm-svn: 187828
 2013-08-06 23:01:10 +00:00
Akira Hatanaka e2a39e7532 [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias' 
EmitAlias flag and have MipsInstPrinter::printAlias print the aliases.

llvm-svn: 187824
 2013-08-06 22:35:29 +00:00
Akira Hatanaka 34a32c0b87 [mips] Replace usages of register classes with register operands. Also, remove 
unnecessary jalr InstAliases in Mips64InstrInfo.td and add the code to print
jalr InstAliases in MipsInstPrinter::printAlias.

llvm-svn: 187821
 2013-08-06 22:20:40 +00:00
Akira Hatanaka 21f334372e [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also, 
remove lines that are setting DecoderNamespace for pseudo atomic instructions.

No intended functionality change.

llvm-svn: 187632
 2013-08-01 23:14:16 +00:00
Akira Hatanaka d6445686a9 [mips] Rename instruction DANDi to ANDi64. 
No functionality change.

llvm-svn: 187469
 2013-07-31 00:57:41 +00:00
Akira Hatanaka f8fff213d5 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.

llvm-svn: 187468
 2013-07-31 00:55:34 +00:00
Akira Hatanaka 44ff81d4e3 [mips] Use ADDu instead of OR to copy general purpose registers. Also, delete 
the InstAlias pattern which maps "move" to OR to resolve ambiguity in
MatchTable.

llvm-svn: 186855
 2013-07-22 18:52:22 +00:00
Akira Hatanaka 1baf2ea2d1 [mips] Add instruction itinerary classes for mult, seb and slt instructions. 
llvm-svn: 186222
 2013-07-12 22:43:20 +00:00
Akira Hatanaka b34ad7860f [mips] Add new InstrItinClasses for move from/to coprocessor instructions and 
floating point loads and stores.

No changes in functionality.

llvm-svn: 185399
 2013-07-02 00:00:02 +00:00
Akira Hatanaka 6871031be9 [mips] Add instruction selection patterns for blez and bgez. 
llvm-svn: 182396
 2013-05-21 17:13:47 +00:00
Akira Hatanaka 1cb024207f [mips] Trap on integer division by zero. 
By default, a teq instruction is inserted after integer divide. No divide-by-zero
checks are performed if option "-mnocheck-zero-division" is used.

llvm-svn: 182306
 2013-05-20 18:07:43 +00:00
Jack Carter 51785c4715 Mips assembler: Add branch macro definitions 
This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows:
bnez $rs,$imm => bne $rs,$zero,$imm
beqz $rs,$imm => beq $rs,$zero,$imm

The corresponding test cases are added.

Patch by Vladimir Medic

llvm-svn: 182040
 2013-05-16 19:40:19 +00:00
Akira Hatanaka 4254319ef9 [mips] Fix handling of instructions which copy to/from accumulator registers. 
Expand copy instructions between two accumulator registers before callee-saved
scan is done. Handle copies between integer GPR and hi/lo registers in
MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not
needed.

llvm-svn: 180827
 2013-04-30 23:22:09 +00:00
Akira Hatanaka be8612f6f4 [mips] Fix definitions of multiply, multiply-add/sub and divide instructions. 
The new instructions have explicit register output operands and use table-gen
patterns instead of C++ code to do instruction selection.

Mips16's instructions are unaffected by this change.

llvm-svn: 178403
 2013-03-30 01:36:35 +00:00
Akira Hatanaka c8d85025a0 [mips] Define pseudo instructions for spilling and copying accumulator 
registers.

llvm-svn: 178390
 2013-03-30 00:54:52 +00:00
Jack Carter 311246c6d5 [Mips Assembler] Add support for OR macro with imediate opperand 
Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic
llvm-svn: 178316
 2013-03-28 23:45:13 +00:00
Jack Carter e1d85d55e6 [Mips Assembler] Add alias definitions for jal 
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic
llvm-svn: 178304
 2013-03-28 23:02:21 +00:00
Akira Hatanaka c7828356aa [mips] Print move instructions. 
"move $4, $5" is printed instead of "or $4, $5, $zero".

llvm-svn: 176455
 2013-03-04 22:25:01 +00:00
Akira Hatanaka 061d1ea5da [mips] Add definition of JALR instruction which has two register operands. Change the 
original JALR instruction with one register operand to be a pseudo-instruction.

llvm-svn: 174657
 2013-02-07 19:48:00 +00:00
Jack Carter 9c1a027fe8 This patch that sets the EmitAlias flag in td files 
and enables the instruction printer to print aliased 
instructions. 

Due to usage of RegisterOperands a change in common 
code (utils/TableGen/AsmWriterEmitter.cpp) is required 
to get the correct register value if it is a RegisterOperand.

Contributer: Vladimir Medic
 
llvm-svn: 174358
 2013-02-05 08:32:10 +00:00
Jack Carter 86c2c564ff This is a resubmittal. For some reason it broke the bots yesterday 
but I cannot reproduce the problem and have scrubed my sources and
even tested with llvm-lit -v --vg.

Removal of redundant code and formatting fixes.

Contributers: Jack Carter/Vladimir Medic
 
llvm-svn: 172842
 2013-01-18 20:15:06 +00:00
Jack Carter 873c724b4a This patch tackles the problem of parsing Mips 
register names in the standalone assembler llvm-mc.

Registers such as $A1 can represent either a 32 or
64 bit register based on the instruction using it.
In addition, based on the abi, $T0 can represent different
32 bit registers.


The problem is resolved by the Mips specific AsmParser 
td definitions changing to work together. Many cases of
RegisterClass parameters are now RegisterOperand.


Contributer: Vladimir Medic
llvm-svn: 172284
 2013-01-12 01:03:14 +00:00
Craig Topper a8c5ec09c7 Remove # from the beginning and end of def names. The # is a paste operator and should only be used with something to paste on either side. 
llvm-svn: 171697
 2013-01-07 05:45:56 +00:00
Akira Hatanaka e067e5a13f [mips] 80 columns. 
llvm-svn: 171515
 2013-01-04 19:38:05 +00:00
Akira Hatanaka f412e7501a [mips] Reorder template parameters. Remove class shift_rotate_imm32 and 
shift_rotate_imm64.

llvm-svn: 171513
 2013-01-04 19:25:46 +00:00
Akira Hatanaka e36e2f6876 [mips] Refactor instructions which move data from or to coprocessors. 
llvm-svn: 171510
 2013-01-04 19:13:49 +00:00
Akira Hatanaka 6ac2fc4976 [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware 
instructions.

llvm-svn: 170956
 2012-12-21 23:21:32 +00:00
Akira Hatanaka beea8a34c3 [mips] Refactor SYNC and multiply/divide instructions. 
llvm-svn: 170955
 2012-12-21 23:17:36 +00:00
Akira Hatanaka a158042a56 [mips] Refactor jump, jump register, jump-and-link and nop instructions. 
llvm-svn: 170952
 2012-12-21 23:03:50 +00:00
Akira Hatanaka e1826d7464 [mips] Refactor load/store left/right and load-link and store-conditional 
instructions.

llvm-svn: 170950
 2012-12-21 23:01:24 +00:00
Akira Hatanaka d9bf8424e5 [mips] Refactor load/store instructions. 
llvm-svn: 170948
 2012-12-21 22:58:55 +00:00
Akira Hatanaka e738efc95b [mips] Refactor LUI instruction. 
llvm-svn: 170944
 2012-12-21 22:46:07 +00:00
Akira Hatanaka 895e1cb2aa [mips] Refactor count leading zero or one instructions. 
llvm-svn: 170942
 2012-12-21 22:43:58 +00:00
Akira Hatanaka 4f4c4aa05e [mips] Refactor sign-extension-in-register instructions. 
llvm-svn: 170940
 2012-12-21 22:41:52 +00:00
Akira Hatanaka b14c6e4e5f [mips] Refactor instructions which copy from and to HI/LO registers. 
llvm-svn: 170939
 2012-12-21 22:39:17 +00:00
Akira Hatanaka 9e89195dce [mips] Refactor logical NOR instructions. 
llvm-svn: 170937
 2012-12-21 22:35:47 +00:00
Akira Hatanaka e7f1acc7c0 [mips] Refactor SLT (set on less than) instructions. Separate encoding 
information from the rest. 

llvm-svn: 170664
 2012-12-20 04:27:52 +00:00
Akira Hatanaka b1527b7505 [mips] Remove asm string parameter from pseudo instructions. Add InstrItinClass 
parameter.

llvm-svn: 170661
 2012-12-20 04:20:09 +00:00
Akira Hatanaka c0ea0bb99b [mips] Refactor conditional branch instructions with one register operand. 
Separate encoding information from the rest.

llvm-svn: 170659
 2012-12-20 04:13:23 +00:00
Akira Hatanaka f71ffd29d9 [mips] Refactor conditional branch instructions with two register operands. 
Separate encoding information from the rest.

llvm-svn: 170657
 2012-12-20 04:10:13 +00:00
Akira Hatanaka 7d75f9e3d3 [mips] Change the order of template parameters. Move the default parameters to 
the end. 

llvm-svn: 170651
 2012-12-20 03:52:08 +00:00
Akira Hatanaka 244f9e874c [mips] Refactor shift instructions with register operands. Separate encoding 
information from the rest.

llvm-svn: 170650
 2012-12-20 03:48:24 +00:00
Akira Hatanaka 7f96ad325f [mips] Refactor shift immediate instructions. Separate encoding information 
from the rest.

llvm-svn: 170649
 2012-12-20 03:44:41 +00:00
Akira Hatanaka ab1b715bf2 [mips] Refactor arithmetic and logic instructions with immediate operands. 
Separate encoding information from the rest.

llvm-svn: 170648
 2012-12-20 03:40:03 +00:00