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247 Commits

Author SHA1 Message Date
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Evan Cheng 97e6428014 Change VFPNeonA8 definition to make the code easier to read. 
llvm-svn: 126298
 2011-02-23 02:35:33 +00:00
Evan Cheng 04ad35b53f VFP single precision arith instructions can go down to NEON pipeline, but on Cortex-A8 only. 
llvm-svn: 126238
 2011-02-22 19:53:14 +00:00
Bruno Cardoso Lopes 9cd43977c3 Add assembly parsing support for "msr" and also fix its encoding. Also add 
testcases for the disassembler to make sure it still works for "msr".

llvm-svn: 125948
 2011-02-18 19:45:59 +00:00
Evan Cheng 4a8c43fe6d Some single precision VFP instructions may be executed on NEON pipeline, but not double precision ones. 
llvm-svn: 125624
 2011-02-16 00:35:02 +00:00
Bruno Cardoso Lopes 90d1dfe4c6 Fix encoding and add parsing support for the arm/thumb CPS instruction: 
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
  from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
  wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.

llvm-svn: 125489
 2011-02-14 13:09:44 +00:00
Jim Grosbach 861e49ce3b AsmMatcher custom operand parser failure enhancements. 
Teach the AsmMatcher handling to distinguish between an error custom-parsing
an operand and a failure to match. The former should propogate the error
upwards, while the latter should continue attempting to parse with
alternative matchers.

Update the ARM asm parser accordingly.

llvm-svn: 125426
 2011-02-12 01:34:40 +00:00
Bruno Cardoso Lopes 36dd43fda6 Add support for parsing dmb/dsb instructions 
llvm-svn: 125055
 2011-02-07 22:09:15 +00:00
Bruno Cardoso Lopes 4d4b490fb7 Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes cf99dc7eb9 Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Jim Grosbach ec86bac8b3 Add a FIXME. 
llvm-svn: 123769
 2011-01-18 19:59:19 +00:00
Jim Grosbach d42257ceef The new t2LEApcrel* pseudo instructions need the size specified. 
rdar://8768390

llvm-svn: 121876
 2010-12-15 18:48:45 +00:00
Owen Anderson b538a22762 Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends. 
llvm-svn: 121585
 2010-12-10 22:32:08 +00:00
Jim Grosbach 95bd6b7b62 Tidy up. 
llvm-svn: 121522
 2010-12-10 20:51:35 +00:00
Jim Grosbach c4669edf2c Trailing whitespace. 
llvm-svn: 121521
 2010-12-10 20:47:29 +00:00
Owen Anderson cf096a431a Fix Thumb2 encoding of the S bit. 
llvm-svn: 121182
 2010-12-07 20:50:15 +00:00
Jim Grosbach 0bfb4d5043 The ARM AsmMatcher needs to know that the CCOut operand is a register value, 
not an immediate. It stores either ARM::CPSR or reg0.

llvm-svn: 121018
 2010-12-06 18:21:12 +00:00
Bill Wendling 87240d4b9c Add a post encoder method to the VFP instructions to convert them to the Thumb2 
encoding if we're in that mode.

llvm-svn: 120608
 2010-12-01 21:54:50 +00:00
Owen Anderson 943fb60b1f Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax. 
llvm-svn: 120589
 2010-12-01 19:18:46 +00:00
Bill Wendling cbb08ca08c General cleanups of comments. 
llvm-svn: 120536
 2010-12-01 02:42:55 +00:00
Bill Wendling c25545a1a7 s/T1pIEncode/T1pILdStEncode/g 
s/T1pIEncodeImm/T1pILdStEncodeImm/g

llvm-svn: 120524
 2010-12-01 01:38:08 +00:00
Bill Wendling 7c646b924b Renaming variables to coincide with documentation. No functionality change. 
llvm-svn: 120522
 2010-12-01 01:32:02 +00:00
Bill Wendling 05632cb5cc Rename operands to match ARM documentation. No functionality change. 
llvm-svn: 120500
 2010-11-30 23:54:45 +00:00
Bill Wendling 5c51fcda81 Inline classes that were used in only one place. 
llvm-svn: 120488
 2010-11-30 23:16:25 +00:00
Bill Wendling a9e3df7aa0 * Add support for encoding t_addrmode_s2 and t_addrmode_s1. They are the same as 
t_addrmode_s4, but with a different scaling factor.

* Encode the Thumb1 load and store instructions. This involved a bit of
  refactoring (hi, Chris! :-). Some of the patterns became dead afterwards and
  were removed.

llvm-svn: 120482
 2010-11-30 22:57:21 +00:00
Jim Grosbach cd5e30f6c6 Pseudo-ize BX_CALL and friends. Remove dead instruction format classes. 
rdar://8685712

llvm-svn: 120438
 2010-11-30 18:30:19 +00:00
Owen Anderson e22c7322b8 Correct Thumb2 encodings for a much wider range of loads and stores. 
llvm-svn: 120364
 2010-11-30 00:14:31 +00:00
Jim Grosbach 0c51bb4b25 Parameterize ARMPseudoInst size property. 
llvm-svn: 120353
 2010-11-29 23:48:41 +00:00
Jim Grosbach 58bc36a3a9 ARM Pseudo-ize tBR_JTr. 
llvm-svn: 120310
 2010-11-29 19:32:47 +00:00
Jim Grosbach 150b1ad7f8 Switch ARM BR_JTm and BR_JTr instructions to be MC-expanded pseudos. 
llvm-svn: 120303
 2010-11-29 18:37:44 +00:00
Jim Grosbach 5876e41c9f trailing whitespace 
llvm-svn: 119863
 2010-11-19 22:42:55 +00:00
Jim Grosbach 09d7bfd886 Add ARM encoding information for STRD. 
llvm-svn: 119852
 2010-11-19 22:14:31 +00:00
Jim Grosbach 6e9aace4f3 Factor out operand encoding bits for ARM addressing mode 2 store instructions. 
llvm-svn: 119846
 2010-11-19 21:35:06 +00:00
Jim Grosbach 09f6823eb6 Delete another dead class. 
llvm-svn: 119844
 2010-11-19 21:16:08 +00:00
Jim Grosbach e093e5f0dc whitespace tweak. 
llvm-svn: 119843
 2010-11-19 21:14:37 +00:00
Jim Grosbach d6e5c9f2fe Refactor PICSTR* instructions to really be pseudos. Nuke dead classes. 
llvm-svn: 119841
 2010-11-19 21:14:02 +00:00
Jim Grosbach 4a22eba616 Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes. 
llvm-svn: 119840
 2010-11-19 21:07:51 +00:00
Jim Grosbach 003c6e700b Add ARM binary encoding information for the rest of the indexed loads. 
llvm-svn: 119821
 2010-11-19 19:41:26 +00:00
Jim Grosbach c6ac246671 Remove dead code. 
llvm-svn: 119815
 2010-11-19 18:18:37 +00:00
Jim Grosbach 76aed40813 ARM LDRD binary encoding. 
llvm-svn: 119812
 2010-11-19 18:16:46 +00:00
Jim Grosbach 1b91ae18ed Add ARM encoding information for LDRH post-increment. 
llvm-svn: 119743
 2010-11-18 21:43:37 +00:00
Owen Anderson 3625098459 Fill out the set of Thumb2 multiplication operator encodings. 
llvm-svn: 119733
 2010-11-18 20:32:18 +00:00
Jim Grosbach 51fdc47a11 ARMPseudoInst instructions should default to being considered a single 4-byte 
instruction. Any that may be expanded otherwise by MC lowering should
override this value. rdar://8683274

llvm-svn: 119713
 2010-11-18 18:01:40 +00:00
Jim Grosbach a74c7ccd59 ARM PseudoInst instructions don't need or use an assembler string. Get rid of 
the operand to the pattern.

llvm-svn: 119607
 2010-11-18 01:38:26 +00:00
Jim Grosbach 19be1fbca1 Add FIXME. 
llvm-svn: 119603
 2010-11-18 01:20:48 +00:00
Jim Grosbach cfb66204b7 Refactor the ARM PICADD and PICLDR* instructions to really be pseudos and not 
just pretend to be.

llvm-svn: 119602
 2010-11-18 01:15:56 +00:00
Jim Grosbach 8e7f8df4a2 Refactor a few ARM load instructions to better parameterize things and re-use 
common encoding information.

llvm-svn: 119598
 2010-11-18 00:46:58 +00:00
Jim Grosbach 8839775df6 More ARM encoding bits. LDRH now encodes properly. 
llvm-svn: 119529
 2010-11-17 18:11:11 +00:00
Bill Wendling 345b48fcbd Add binary emission stuff for VLDM/VSTM. This reuses the 
"getRegisterListOpValue" logic. If the registers are double or single precision,
the value returned is suitable for VLDM/VSTM.

llvm-svn: 119435
 2010-11-17 00:45:23 +00:00
Bill Wendling 3bd60eff26 - Remove dead patterns. 
- Add encodings to the *LDMIA_RET instrs. Probably not needed...

llvm-svn: 119323
 2010-11-16 02:08:45 +00:00