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4915 Commits

Author SHA1 Message Date
Evan Cheng 91c574b642 New type v2f32. 
llvm-svn: 26435
 2006-03-01 01:06:22 +00:00
Evan Cheng 0e69f45b07 Another entry. 
llvm-svn: 26430
 2006-02-28 23:38:49 +00:00
Evan Cheng 990c3602bd Don't match x << 1 to LEAL. It's better to emit x + x. 
llvm-svn: 26429
 2006-02-28 21:13:57 +00:00
Chris Lattner b9f35f06bc Add a subtarget feature for the stfiwx instruction. I know the G5 has it, 
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

llvm-svn: 26421
 2006-02-28 07:08:22 +00:00
Chris Lattner 872810da6c remove implemented item 
llvm-svn: 26418
 2006-02-28 06:36:04 +00:00
Nate Begeman f918ed2e33 readme updates 
llvm-svn: 26405
 2006-02-27 22:08:36 +00:00
Chris Lattner ec185f7843 Don't print constant initializers, they may span lines now. 
llvm-svn: 26403
 2006-02-27 20:09:23 +00:00
Jim Laskey 8f2c1021b4 Removed dependency on how operands are printed (want multi-line.) 
llvm-svn: 26399
 2006-02-27 10:29:04 +00:00
Chris Lattner ab8164042a Implement bit propagation through sub nodes, this (re)implements 
PowerPC/div-2.ll

llvm-svn: 26392
 2006-02-27 01:00:42 +00:00
Chris Lattner a60751dd43 Check RHS simplification before LHS simplification to avoid infinitely looping 
on PowerPC/small-arguments.ll

llvm-svn: 26389
 2006-02-27 00:36:27 +00:00
Chris Lattner 27220f8958 Just like we use the RHS of an AND to simplify the LHS, use the LHS to 
simplify the RHS.  This allows for the elimination of many thousands of
ands from multisource, and compiles CodeGen/PowerPC/and-elim.ll:test2
into this:

_test2:
        srwi r2, r3, 1
        xori r3, r2, 40961
        blr

instead of this:

_test2:
        rlwinm r2, r3, 31, 17, 31
        xori r2, r2, 40961
        rlwinm r3, r2, 0, 16, 31
        blr

llvm-svn: 26388
 2006-02-27 00:22:28 +00:00
Chris Lattner 118ddba929 Add a bunch of missed cases. Perhaps the most significant of which is that 
assertzext produces zero bits.

llvm-svn: 26386
 2006-02-26 23:36:02 +00:00
Evan Cheng 877ab55e06 ConstantPoolIndex is now the displacement portion of the address (rather 
than base).

llvm-svn: 26382
 2006-02-26 09:12:34 +00:00
Evan Cheng 75b8783aaf Fixed ConstantPoolIndex operand asm print bug. This fixed 2005-07-17-INT-To-FP 
and 2005-05-12-Int64ToFP.

llvm-svn: 26380
 2006-02-26 08:28:12 +00:00
Evan Cheng 77d86ff8fc * Cleaned up addressing mode matching code. 
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
  they need to be matched before LEA.

llvm-svn: 26376
 2006-02-25 10:09:08 +00:00
Evan Cheng 1c557bfeb5 Updates. 
llvm-svn: 26375
 2006-02-25 10:04:07 +00:00
Evan Cheng 1fac3b3360 * Allow mul, shl nodes to be codegen'd as LEA (if appropriate). 
* Add patterns to handle GlobalAddress, ConstantPool, etc.
  MOV32ri to materialize these nodes in registers.
  ADD32ri to handle %reg + GA, etc.
  MOV32mi to handle store GA, etc. to memory.

llvm-svn: 26374
 2006-02-25 10:02:21 +00:00
Evan Cheng e4a8b74e4f ConstantPoolIndex is now the displacement field of addressing mode. 
llvm-svn: 26373
 2006-02-25 09:56:50 +00:00
Evan Cheng 994700101e Added a common about the need for X86ISD::Wrapper. 
llvm-svn: 26372
 2006-02-25 09:55:19 +00:00
Evan Cheng ed169db8a5 Added an offset field to ConstantPoolSDNode. 
llvm-svn: 26371
 2006-02-25 09:54:52 +00:00
Evan Cheng 42d5ac557c Fix an obvious bug exposed when we are doing 
ADD X, 4
==>
MOV32ri $X+4, ...

llvm-svn: 26366
 2006-02-25 01:37:02 +00:00
Chris Lattner 7674d90fa1 Add memory printing support for PPC. Input memory operands now work with 
inline asms! :)

llvm-svn: 26365
 2006-02-24 20:27:40 +00:00
Chris Lattner a1ec1ddd59 Implement selection of inline asm memory operands 
llvm-svn: 26348
 2006-02-24 02:13:12 +00:00
Chris Lattner 2a9e1e3e74 Recognize memory operand codes 
llvm-svn: 26345
 2006-02-24 01:10:46 +00:00
Evan Cheng 0ed48fe601 PPC JIT relocation model should be DynamicNoPIC. 
llvm-svn: 26338
 2006-02-23 22:18:07 +00:00
Evan Cheng e0ed6ec13f - Clean up the lowering and selection code of ConstantPool, GlobalAddress, 
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
  mentioned leaf nodes. Do not mutate and nodes and do not record the
  selection in CodeGenMap. These nodes should be safe to duplicate. This is
  a performance win.

llvm-svn: 26335
 2006-02-23 20:41:18 +00:00
Chris Lattner 1bad2546d0 Implement the PPC inline asm "L" modifier. This allows us to compile: 
long long test(long long X) {
  __asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
  return X;
}

to:
        foo r2 r3 r2 r3

llvm-svn: 26333
 2006-02-23 19:31:10 +00:00
Chris Lattner 16f08f53b1 "." isn't enough to get a private label on linux, use ".L". 
llvm-svn: 26327
 2006-02-23 05:25:02 +00:00
Chris Lattner 2bacf981bf add a small and simple case. 
llvm-svn: 26326
 2006-02-23 05:17:43 +00:00
Evan Cheng f4448cee66 A couple of new entries. 
llvm-svn: 26325
 2006-02-23 02:50:21 +00:00
Evan Cheng 1f342c2884 PIC related bug fixes. 
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.

llvm-svn: 26324
 2006-02-23 02:43:52 +00:00
Evan Cheng 7eabbfd618 X86 codegen tweak to use lea in another case: 
Suppose base == %eax and it has multiple uses, then instead of
  movl %eax, %ecx
  addl $8, %ecx
use
  leal 8(%eax), %ecx.

llvm-svn: 26323
 2006-02-23 00:13:58 +00:00
Evan Cheng 7714a59d91 Missing .globl for weak / link-once .text symbols. 
llvm-svn: 26321
 2006-02-22 23:59:57 +00:00
Chris Lattner 2e124af406 Don't return registers from register classes that aren't legal. 
llvm-svn: 26317
 2006-02-22 23:00:51 +00:00
Evan Cheng 73136dfecc - Added option -relocation-model to set relocation model. Valid values include static, pic, 
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.

llvm-svn: 26315
 2006-02-22 20:19:42 +00:00
Jim Laskey 2fa33a989d Coordinate activities with llvm-gcc4 and dwarf. 
llvm-svn: 26314
 2006-02-22 19:02:11 +00:00
Evan Cheng 9e252e3bcf Added MMX, SSE1, and SSE2 vector instructions and some simple patterns. 
Fixed some existing bugs (wrong predicates, prefixes) at the same time.

llvm-svn: 26310
 2006-02-22 02:26:30 +00:00
Chris Lattner 7ad77dfc2a split register class handling from explicit physreg handling. 
llvm-svn: 26308
 2006-02-22 00:56:39 +00:00
Chris Lattner 7bb4696dc3 Updates to match change of getRegForInlineAsmConstraint prototype 
llvm-svn: 26305
 2006-02-21 23:11:00 +00:00
Evan Cheng d58478161f One more round of reorg so sabre doesn't freak out. :-) 
llvm-svn: 26303
 2006-02-21 20:00:20 +00:00
Evan Cheng 6fc1162855 A big more cleaning up. 
llvm-svn: 26302
 2006-02-21 19:30:30 +00:00
Evan Cheng 8711b6bff3 Moving things to their proper places. 
llvm-svn: 26301
 2006-02-21 19:26:52 +00:00
Evan Cheng 6e595b9fd8 Split instruction info into multiple files, one for each of x87, MMX, and SSE. 
llvm-svn: 26300
 2006-02-21 19:13:53 +00:00
Chris Lattner 0a08f44704 missed optzn 
llvm-svn: 26299
 2006-02-21 18:29:44 +00:00
Chris Lattner 747cf60696 The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter 
instructions are expensive.

llvm-svn: 26298
 2006-02-21 18:04:32 +00:00
Evan Cheng d57203c0a1 Added separate alias instructions for SSE logical ops that operate on non-packed types. 
llvm-svn: 26297
 2006-02-21 02:24:38 +00:00
Evan Cheng afffe63fc1 Added MMX and XMM packed integer move instructions, movd and movq. 
llvm-svn: 26296
 2006-02-21 01:39:57 +00:00
Evan Cheng fa57a0add9 Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64. 
Added generic vector types: VR64 and VR128.

llvm-svn: 26295
 2006-02-21 01:38:21 +00:00
Evan Cheng 43070b7541 Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
 2006-02-20 22:34:53 +00:00
Evan Cheng 4547400ae2 Some updates 
llvm-svn: 26292
 2006-02-20 19:58:27 +00:00
Evan Cheng d13778eb30 If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take 
advantage of fisttpll.

llvm-svn: 26288
 2006-02-18 07:26:17 +00:00
Nate Begeman 983ca89714 Add a fold for add that exchanges it with a constant shift if possible, so 
that the shift may be more easily folded into other operations.

llvm-svn: 26286
 2006-02-18 02:43:25 +00:00
Evan Cheng 70af620709 Added fisttp for fp to int conversion. 
llvm-svn: 26283
 2006-02-18 02:36:28 +00:00
Evan Cheng 06c2e6d1b3 Disable PIC for JIT. 
llvm-svn: 26281
 2006-02-18 01:49:25 +00:00
Evan Cheng 5caed8a231 Jit does not support PIC yet. 
llvm-svn: 26278
 2006-02-18 00:57:10 +00:00
Evan Cheng 5588de9415 x86 / Darwin PIC support. 
llvm-svn: 26273
 2006-02-18 00:15:05 +00:00
Evan Cheng 5f99760ae7 Moved PICEnabled to include/llvm/Target/TargetOptions.h 
llvm-svn: 26272
 2006-02-18 00:08:58 +00:00
Chris Lattner 07a2677e43 unbreak the build 
llvm-svn: 26260
 2006-02-17 07:09:27 +00:00
Evan Cheng 593bea73ba Unbreak x86 be 
llvm-svn: 26259
 2006-02-17 07:01:52 +00:00
Nate Begeman 5965bd19f8 kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC 
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.

llvm-svn: 26255
 2006-02-17 05:43:56 +00:00
Chris Lattner 67c21b6c46 add note about div by power of 2 
llvm-svn: 26253
 2006-02-17 04:20:13 +00:00
Jeff Cohen 0d62ebd13f Fix bug noticed by VC++. 
llvm-svn: 26252
 2006-02-17 02:12:18 +00:00
Nate Begeman 3920ce4d8d Whoops, didn't mean to check this in yet. 
llvm-svn: 26250
 2006-02-17 00:56:19 +00:00
Nate Begeman 4a0dc0c8f6 Add a missing and useful pat frag 
llvm-svn: 26249
 2006-02-17 00:51:06 +00:00
Evan Cheng b590d3a72b Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers" 
issue. Need to do more experiments.

llvm-svn: 26247
 2006-02-17 00:04:28 +00:00
Nate Begeman 7e5496d5fe Kill the x86 pattern isel. boom. 
llvm-svn: 26246
 2006-02-17 00:03:04 +00:00
Evan Cheng db1dbbe8d6 Remove the entry about using movapd for SSE reg-reg moves. 
llvm-svn: 26245
 2006-02-17 00:00:58 +00:00
Evan Cheng eb7b3380fd pxor (for FLD0SS) encoding was missing the OpSize prefix. 
llvm-svn: 26244
 2006-02-16 23:59:30 +00:00
Chris Lattner 936cc9fe53 Remove the skeleton target, it doesn't produce useful code and there are 
other small targets that do that can be learned from.  They also have
the added advantage of being tested :)

llvm-svn: 26243
 2006-02-16 23:14:50 +00:00
Evan Cheng 24c461b51e 1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This 
proves to be worth 20% on Ptrdist/ks. Might be related to dependency
   breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
   are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
   spill / restore FsMOVAPSrr and FsMOVAPDrr.

llvm-svn: 26241
 2006-02-16 22:45:17 +00:00
Evan Cheng 3f99628939 Use movaps / movapd to spill / restore V4F4 / V2F8 registers. 
llvm-svn: 26240
 2006-02-16 21:20:26 +00:00
Nate Begeman 8a77efe4f7 Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
 2006-02-16 21:11:51 +00:00
Evan Cheng 01afec2adb MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg. 
llvm-svn: 26234
 2006-02-16 19:34:41 +00:00
Duraid Madina 36a2ee299e distinguish between objects and register names, now we can have stuff 
with names like "f84", "in6" etc etc.

this should fix one or two tests

llvm-svn: 26232
 2006-02-16 13:12:57 +00:00
Evan Cheng 42c01c8d39 If the false case is the current basic block, then this is a self loop. 
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop.  Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.

Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.

llvm-svn: 26231
 2006-02-16 08:27:56 +00:00
Evan Cheng ae82498e81 Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg 
transfer.

According to the Intel P4 Optimization Manual:

Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.

Not to mention movaps is shorter than movss.

llvm-svn: 26226
 2006-02-16 01:50:02 +00:00
Evan Cheng 03c1e6f48e A bit more memset / memcpy optimization. 
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).

llvm-svn: 26224
 2006-02-16 00:21:07 +00:00
Evan Cheng 76a7775ce1 Remove an entry. 
llvm-svn: 26222
 2006-02-15 22:14:34 +00:00
Chris Lattner 6afb5587da new test 
llvm-svn: 26217
 2006-02-15 19:52:06 +00:00
Chris Lattner 6db414e8de Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires 
it, because this:

.bss
X:
.byte 0

results in the assembler warning: "initialization in bss segment".  Annoying.

llvm-svn: 26204
 2006-02-15 07:07:14 +00:00
Chris Lattner a9d0b5800a Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc. 
The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.

llvm-svn: 26202
 2006-02-15 06:41:34 +00:00
Evan Cheng 7a6c21ac26 Remove an entry. 
llvm-svn: 26197
 2006-02-15 01:56:48 +00:00
Evan Cheng 2d23c9f1ab Use .zerofill on x86/darwin. 
llvm-svn: 26196
 2006-02-15 01:56:23 +00:00
Evan Cheng aacc4c3b4c cvtsd2ss / cvtss2sd encoding bug. 
llvm-svn: 26193
 2006-02-15 00:31:03 +00:00
Evan Cheng 665c26ab40 movaps, movapd encoding bug. 
llvm-svn: 26192
 2006-02-15 00:11:37 +00:00
Chris Lattner e3c793a71a new note 
llvm-svn: 26186
 2006-02-14 22:19:54 +00:00
Chris Lattner b134520b86 If we have zero initialized data with external linkage, use .zerofill to 
emit it (instead of .space), saving a bit of space in the .o file.

For example:
int foo[100];
int bar[100] = {};

when compiled with C++ or -fno-common results in shrinkage from 1160 to 360
bytes of space.  The X86 backend can also do this on darwin.

llvm-svn: 26185
 2006-02-14 22:18:23 +00:00
Evan Cheng f84774ed46 Don't special case XS, XD prefixes. 
llvm-svn: 26183
 2006-02-14 21:52:51 +00:00
Evan Cheng fb7b5ef74b Bug fix: XS, XD prefixes were being emitted twice. 
XMM registers were not being handled.

llvm-svn: 26182
 2006-02-14 21:45:24 +00:00
Chris Lattner 84fb09eba4 Make sure that weak functions are aligned properly 
llvm-svn: 26181
 2006-02-14 20:42:33 +00:00
Evan Cheng 43b72f4421 Duh 
llvm-svn: 26180
 2006-02-14 20:37:37 +00:00
Evan Cheng ad8c20cd2b Remove -disable-x86-sse 
llvm-svn: 26179
 2006-02-14 20:30:14 +00:00
Evan Cheng 4b40a42653 Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
llvm-svn: 26174
 2006-02-14 08:38:30 +00:00
Evan Cheng f976d79f78 Add a entry. 
llvm-svn: 26173
 2006-02-14 08:25:32 +00:00
Evan Cheng 6a37456d73 Set maxStoresPerMemSet to 16. Ditto for maxStoresPerMemCpy and 
maxStoresPerMemMove. Although the last one is not used.

llvm-svn: 26172
 2006-02-14 08:25:08 +00:00
Evan Cheng 40b6eb9973 Enable SSE (for the right subtargets) 
llvm-svn: 26169
 2006-02-14 08:07:58 +00:00
Chris Lattner d2d174dd0e Another hack due to allowing multiple symbols with the same name. 
llvm-svn: 26150
 2006-02-13 22:22:42 +00:00
Andrew Lenharth a438ef0ee7 improved zap discovery 
llvm-svn: 26148
 2006-02-13 18:52:29 +00:00
Chris Lattner 62c3484e43 Switch targets over to using SelectionDAG::getCALLSEQ_START to create 
CALLSEQ_START nodes.

llvm-svn: 26143
 2006-02-13 09:00:43 +00:00
Chris Lattner 3a0ad47b39 Switch to using getCALLSEQ_START instead of using our own creation calls 
llvm-svn: 26142
 2006-02-13 08:55:29 +00:00
Nate Begeman bc3ec1d37b Add missing patterns for andi. and andis., fixing test/Regression/CodeGen/ 
PowerPC/and-imm.ll

llvm-svn: 26136
 2006-02-12 09:09:52 +00:00
Duraid Madina 4698e4f5fe fix storing booleans (grawp missed this one) 
llvm-svn: 26120
 2006-02-11 07:33:17 +00:00
Duraid Madina 0010a92375 now short immediates will get matched (previously constants were all 
triggering movl 64bit imm fat instructions)

llvm-svn: 26119
 2006-02-11 07:32:15 +00:00
Evan Cheng a86ba85dc5 Prevent certain nodes that have already been selected from being folded into 
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.

llvm-svn: 26117
 2006-02-11 02:05:36 +00:00
Evan Cheng 2b6f78b664 Nicer code. :-) 
llvm-svn: 26111
 2006-02-10 22:46:26 +00:00
Evan Cheng d49cc3634e Added X86 isel debugging stuff. 
llvm-svn: 26110
 2006-02-10 22:24:32 +00:00
Chris Lattner fcb8a3aa76 Use the auto-generated call matcher. Remove a broken impl of the frameaddr/returnaddr 
intrinsics.

Autogen frameindex matcher

llvm-svn: 26107
 2006-02-10 07:35:42 +00:00
Chris Lattner 0c4dea4cb2 Update to new-style flags usage, simplifying the .td file 
llvm-svn: 26106
 2006-02-10 06:58:25 +00:00
Evan Cheng 907be3e24c Remove a completed entry; add a new entry about fisttp op 
llvm-svn: 26105
 2006-02-10 05:48:15 +00:00
Evan Cheng 101e4b916a Match tblgen change. 
llvm-svn: 26096
 2006-02-09 22:12:53 +00:00
Chris Lattner 4c0bd5bcdf Done 
llvm-svn: 26091
 2006-02-09 20:00:19 +00:00
Chris Lattner 5259aa1c86 Enable LSR by default for SPARC: it is a clear win. 
llvm-svn: 26090
 2006-02-09 19:59:55 +00:00
Evan Cheng d1b82d8db0 Match getTargetNode() changes (now return SDNode* instead of SDOperand). 
llvm-svn: 26085
 2006-02-09 07:17:49 +00:00
Chris Lattner c75d5b093d add an option to turn on LSR. 
llvm-svn: 26080
 2006-02-09 05:06:36 +00:00
Chris Lattner f6190821da Adjust to MachineConstantPool interface change: instead of keeping a 
value/alignment pair for each constant, keep a value/offset pair.

llvm-svn: 26078
 2006-02-09 04:46:04 +00:00
Chris Lattner ba97264e72 rename fields of constant pool entries 
llvm-svn: 26076
 2006-02-09 04:22:52 +00:00
Chris Lattner 832d78d981 Always pass in an alignment. 
llvm-svn: 26070
 2006-02-09 02:19:16 +00:00
Chris Lattner d94a3d2c8a provide an explicit alignment for cp entries 
llvm-svn: 26069
 2006-02-09 02:15:30 +00:00
Evan Cheng 6dc90ca172 Change Select() from 
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);

llvm-svn: 26067
 2006-02-09 00:37:58 +00:00
Chris Lattner 2e07d6370a Darwin doesn't support #APP/#NO_APP 
llvm-svn: 26066
 2006-02-08 23:42:22 +00:00
Chris Lattner 26e385a623 Rename BSel -> PPCBSel for the benefit of doxygen users. 
Move the methods out of line.
Remove unused Debug.h stuff.
Teach getNumBytesForInstruction to know the size of an inline asm.

llvm-svn: 26064
 2006-02-08 19:33:26 +00:00
Chris Lattner b4fc050f0f add a simple optimization 
llvm-svn: 26062
 2006-02-08 17:47:22 +00:00
Chris Lattner b7e074ab9b more email -> README moving 
llvm-svn: 26054
 2006-02-08 07:12:07 +00:00
Chris Lattner f7b962d7d7 Emit the 'mr' pseudoop for easier reading. 
llvm-svn: 26053
 2006-02-08 06:56:40 +00:00
Chris Lattner 45bb34b715 Add some random notes, not high-prio 
llvm-svn: 26052
 2006-02-08 06:52:06 +00:00
Chris Lattner b97142eec0 Move emails from nate into public places 
llvm-svn: 26051
 2006-02-08 06:43:51 +00:00
Evan Cheng adeb8fb5a2 Fixed a local common symbol bug. 
llvm-svn: 26044
 2006-02-07 23:32:58 +00:00
Evan Cheng ec212fb66d For ELF, .comm takes alignment value as the optional 3rd argument. It must be 
specified in bytes.

llvm-svn: 26043
 2006-02-07 21:54:08 +00:00
Chris Lattner 203b2f1288 Implement getConstraintType for PPC. 
llvm-svn: 26042
 2006-02-07 20:16:30 +00:00
Evan Cheng 5a76680de1 Darwin ABI issues: weak, linkonce, etc. dynamic-no-pic support is complete. 
Also fixed a function stub bug. Added weak and linkonce support for
x86 Linux.

llvm-svn: 26038
 2006-02-07 08:38:37 +00:00
Evan Cheng 227e469c25 Remind myself to add PIC and static asm printer support. 
llvm-svn: 26037
 2006-02-07 08:35:44 +00:00
Chris Lattner 15a6c4c444 Add the simple PPC integer constraints 
llvm-svn: 26027
 2006-02-07 00:47:13 +00:00
Chris Lattner d62a3bfa66 Eliminate the printCallOperand method, using a 'call' modifier on 
printOperand instead.

llvm-svn: 26025
 2006-02-06 23:41:19 +00:00
Chris Lattner 2bf2c8d7e7 Change prototype 
llvm-svn: 26022
 2006-02-06 22:18:19 +00:00
Andrew Lenharth f5b7f16259 see what this allignment thing will do 
llvm-svn: 26017
 2006-02-06 17:15:17 +00:00
Jim Laskey 58d48c8118 We seem to have settled to __DWARF for section name. 
llvm-svn: 26015
 2006-02-06 14:16:15 +00:00
Evan Cheng d5f2ba0d6f - Update load folding checks to match those auto-generated by tblgen. 
- Manually select SDOperand's returned by TryFoldLoad which make up the
  load address.

llvm-svn: 26012
 2006-02-06 06:02:33 +00:00
Evan Cheng bfa4b7cc75 Complex pattern isel code shouldn't select nodes. 
llvm-svn: 26010
 2006-02-05 08:45:01 +00:00
Chris Lattner 463fa70eaa Fix the Sparc backend with Evan's recent tblgen changes 
llvm-svn: 26009
 2006-02-05 08:35:50 +00:00
Chris Lattner 8467e5d6af This xform isn't safe 
llvm-svn: 26007
 2006-02-05 08:26:16 +00:00
Chris Lattner 4b8fcc229f some stuff is done 
llvm-svn: 26004
 2006-02-05 07:54:37 +00:00
Evan Cheng a28b764886 Use SelectRoot() as the entry to any tblgen based isel. 
llvm-svn: 25998
 2006-02-05 06:51:51 +00:00
Evan Cheng 54cb1833a4 Use SelectRoot() as entry of any tblgen based isel. 
llvm-svn: 25997
 2006-02-05 06:46:41 +00:00
Chris Lattner 25777c8c25 Remove the SparcV8 backend. It has been renamed to be the Sparc backend. 
llvm-svn: 25992
 2006-02-05 06:33:29 +00:00
Chris Lattner a3e5b2c61c remove V8 reference 
llvm-svn: 25991
 2006-02-05 06:32:59 +00:00
Chris Lattner 158e1f519c Rename SPARC V8 target to be the LLVM SPARC target. 
llvm-svn: 25985
 2006-02-05 05:50:24 +00:00
Chris Lattner c0e48c6c58 add a note 
llvm-svn: 25984
 2006-02-05 05:27:35 +00:00
Evan Cheng d19d51f414 Re-commit the last bit of change that was backed out. 
llvm-svn: 25983
 2006-02-05 05:25:07 +00:00
Chris Lattner c070cb685d Use getPreferredAlignmentLog. 
llvm-svn: 25980
 2006-02-05 01:45:04 +00:00
Chris Lattner 1b1a8731c0 Use the asmprinter to find out what the preferred alignment of a global is. 
This patch speeds up 172.mgrid from 31.81s to 11.39s on darwin/ppc.
Many many thanks to Nate for tracking down the root cause of the issue.

llvm-svn: 25979
 2006-02-05 01:30:45 +00:00
Andrew Lenharth 1fcff15f86 linkage fix for weak functions 
llvm-svn: 25976
 2006-02-04 19:13:09 +00:00
Chris Lattner 22b4edfb42 Temporarily revert this patch, which probably breaks with the 
tblgen patch reverted.

llvm-svn: 25971
 2006-02-04 09:24:16 +00:00
Evan Cheng ce87cac555 Complex pattern's custom matcher should not call Select() on any operands. 
Select them afterwards if it returns true.

llvm-svn: 25968
 2006-02-04 08:50:49 +00:00
Chris Lattner ab146eae38 Custom lower VAARG for the case when we are doing vaarg(double). In this 
case, the double being loaded may not be 8-byte aligned, so we have to use
our standard bit_convert game.

llvm-svn: 25967
 2006-02-04 08:31:30 +00:00
Chris Lattner a1fa8b1c88 Fix a nasty typo that broke functions with big stack frames. 
llvm-svn: 25966
 2006-02-04 08:04:21 +00:00
Chris Lattner d096b2f3e0 fix a bug in my last checkin 
llvm-svn: 25965
 2006-02-04 07:48:46 +00:00
Nate Begeman a1e895cf97 Remove some stuff that now works 
llvm-svn: 25963
 2006-02-04 07:29:35 +00:00
Chris Lattner 32ed2b45c7 add a note 
llvm-svn: 25962
 2006-02-04 07:07:31 +00:00
Chris Lattner 2c0956bcea Two changes: 
1. Treat FMOVD as a copy instruction, to help with coallescing in V9 mode
2. When in V9 mode, insert FMOVD instead of FpMOVD instructions, as we don't
   ever rewrite FpMOVD instructions into FMOVS instructions, thus we just end
   up with commented out copies!
This should fix a bunch of failures in V9 mode on sparc.

llvm-svn: 25961
 2006-02-04 06:58:46 +00:00
Evan Cheng 0a977c95aa Remove an unnecessary predicate. 
llvm-svn: 25954
 2006-02-04 02:23:01 +00:00
Evan Cheng 11613a5219 Separate FILD and FILD_FLAG, the later is only used for SSE2. It produces a 
flag so it can be flagged to a FST.

llvm-svn: 25953
 2006-02-04 02:20:30 +00:00
Chris Lattner ee1dadbccf implementation of some methods for inlineasm 
llvm-svn: 25951
 2006-02-04 02:13:02 +00:00
Nate Begeman 20a894282d Implement some feedback from sabre 
llvm-svn: 25946
 2006-02-03 22:38:07 +00:00
Nate Begeman dc7bba9ffe Add a framework for eliminating instructions that produces undemanded bits. 
llvm-svn: 25945
 2006-02-03 22:24:05 +00:00
Chris Lattner 81e66abd1e add a note 
llvm-svn: 25944
 2006-02-03 22:06:45 +00:00
Chris Lattner d079dbb9b0 another case Nate came up with 
llvm-svn: 25943
 2006-02-03 22:05:41 +00:00
Chris Lattner 277462e20f add a note 
llvm-svn: 25942
 2006-02-03 21:25:23 +00:00
Chris Lattner a1d312c6ea remove an old comment 
llvm-svn: 25940
 2006-02-03 18:59:39 +00:00
Chris Lattner 23d55f2547 Remove the X86PeepholeOptimizerPass, a truly horrible old hack that is now 
obsolete.  yaay :)

llvm-svn: 25939
 2006-02-03 18:54:24 +00:00
Chris Lattner c408558638 When rewriting frame instructions, emit the appropriate small-immediate 
instruction when possible.

llvm-svn: 25938
 2006-02-03 18:20:04 +00:00
Chris Lattner ca76917388 Teach sparc to fold loads/stores into copies. 
Remove the dead getRegClassForType method
minor formating changes.

llvm-svn: 25936
 2006-02-03 07:06:25 +00:00
Chris Lattner d7d98611ca Implement isLoadFromStackSlot and isStoreToStackSlot 
llvm-svn: 25932
 2006-02-03 06:44:54 +00:00
Chris Lattner a23b04acdb remove some target-indep and implemented notes 
llvm-svn: 25930
 2006-02-03 06:22:11 +00:00
Chris Lattner d1aaee03ce target independent notes 
llvm-svn: 25929
 2006-02-03 06:21:43 +00:00
Nate Begeman fc567d85d5 Flesh out a couple of the items in the README 
llvm-svn: 25928
 2006-02-03 05:17:06 +00:00
Andrew Lenharth 1318240fd0 isStoreToStackSlot 
llvm-svn: 25925
 2006-02-03 03:07:37 +00:00
Chris Lattner a1eac9b978 the X86 backend no longer needs to delete its own noop copies 
llvm-svn: 25923
 2006-02-03 02:59:58 +00:00
Chris Lattner f0a2d66d1c Add a note 
llvm-svn: 25921
 2006-02-03 01:49:49 +00:00
Chris Lattner 9b178ce225 update a note 
llvm-svn: 25918
 2006-02-02 23:50:22 +00:00
Nate Begeman 4efb328926 add 64b gpr store to the possible list of isStoreToStackSlot opcodes. 
llvm-svn: 25916
 2006-02-02 21:07:50 +00:00
Chris Lattner 5123346708 fix operand numbers 
llvm-svn: 25915
 2006-02-02 20:38:12 +00:00
Chris Lattner c327d71e06 implement isStoreToStackSlot for PPC 
llvm-svn: 25914
 2006-02-02 20:16:12 +00:00
Chris Lattner bb53acd03c Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :) 
llvm-svn: 25913
 2006-02-02 20:12:32 +00:00
Chris Lattner 246ee44c8f implement isStoreToStackSlot 
llvm-svn: 25911
 2006-02-02 20:00:41 +00:00
Chris Lattner 0acc90c67e add a method 
llvm-svn: 25910
 2006-02-02 19:57:16 +00:00
Chris Lattner d8208c3665 more notes 
llvm-svn: 25908
 2006-02-02 19:43:28 +00:00
Chris Lattner d3f033e8e0 add a note, I have no idea how important this is. 
llvm-svn: 25907
 2006-02-02 19:16:34 +00:00
Chris Lattner e10e1024bc %fcc is not an alias for %fcc0 
llvm-svn: 25906
 2006-02-02 08:02:20 +00:00
Chris Lattner cb34968d19 correct an opcode 
llvm-svn: 25905
 2006-02-02 07:56:15 +00:00
Chris Lattner 9dd7df7ee7 new example 
llvm-svn: 25903
 2006-02-02 07:37:11 +00:00
Nate Begeman cd018525f8 Update the README 
llvm-svn: 25902
 2006-02-02 07:27:56 +00:00
Chris Lattner e0c60d63b1 Implement MaskedValueIsZero for ANY_EXTEND nodes 
llvm-svn: 25900
 2006-02-02 06:43:15 +00:00
Chris Lattner 4b2ec8af23 implemented, testcase here: test/Regression/CodeGen/X86/compare-add.ll 
llvm-svn: 25899
 2006-02-02 06:36:48 +00:00
Evan Cheng d3908f79cb Update. 
llvm-svn: 25896
 2006-02-02 02:40:17 +00:00
Evan Cheng d8fba3a1ee Fix a erroneous comment. 
llvm-svn: 25894
 2006-02-02 00:28:23 +00:00
Chris Lattner 6132a87cf4 more notes 
llvm-svn: 25890
 2006-02-01 23:38:08 +00:00
Evan Cheng b3ea2677a4 Tell codegen MOVAPSrr and MOVAPDrr are copies. 
llvm-svn: 25889
 2006-02-01 23:03:16 +00:00
Evan Cheng f1ed826c2a Added SSE entries to foldMemoryOperand(). 
llvm-svn: 25888
 2006-02-01 23:02:25 +00:00
Evan Cheng 8b40cde148 Rearrange code to my liking. :) 
llvm-svn: 25887
 2006-02-01 23:01:57 +00:00
Chris Lattner f7f056751c add a method 
llvm-svn: 25884
 2006-02-01 22:38:46 +00:00
Chris Lattner 2f7650f9dc another note 
llvm-svn: 25883
 2006-02-01 21:44:48 +00:00
Andrew Lenharth 4b1c726fbb Add immediate forms of cmov and remove some cruft 
llvm-svn: 25882
 2006-02-01 19:37:33 +00:00
Chris Lattner ba56b5dc35 Finegrainify namespacification 
llvm-svn: 25877
 2006-02-01 18:10:56 +00:00
Chris Lattner a983beab37 add a note 
llvm-svn: 25876
 2006-02-01 17:54:23 +00:00
Nate Begeman 7e7f439f85 Fix some of the stuff in the PPC README file, and clean up legalization 
of the SELECT_CC, BR_CC, and BRTWOWAY_CC nodes.

llvm-svn: 25875
 2006-02-01 07:19:44 +00:00
Chris Lattner 3da1bb520e add a note, I'll take care of this after nate commits his big patch 
llvm-svn: 25873
 2006-02-01 06:40:32 +00:00
Evan Cheng 9e350cd6ad - Use xor to clear integer registers (set R, 0). 
- Added a new format for instructions where the source register is implied
  and it is same as the destination register. Used for pseudo instructions
  that clear the destination register.

llvm-svn: 25872
 2006-02-01 06:13:50 +00:00
Evan Cheng c404b5748c Remove another entry. 
llvm-svn: 25871
 2006-02-01 06:08:48 +00:00
Chris Lattner b0a76b0981 Another regression from the pattern isel 
llvm-svn: 25867
 2006-02-01 01:44:25 +00:00
Chris Lattner 7ed3101d14 Beef up the interface to inline asm constraint parsing, making it more general, useful, and easier to use. 
llvm-svn: 25866
 2006-02-01 01:29:47 +00:00
Evan Cheng a24617f5d4 Return's chain should be matching either the chain produced by the 
value or the chain going into the load.

llvm-svn: 25863
 2006-02-01 01:19:32 +00:00
Chris Lattner a0527473ac another testcase. 
llvm-svn: 25862
 2006-02-01 00:28:12 +00:00
Evan Cheng e1ce4d7115 When folding a load into a return of SSE value, check the chain to 
ensure the memory location has not been clobbered.

llvm-svn: 25861
 2006-02-01 00:20:21 +00:00
Evan Cheng bc1fcd074e Remove an item. It's done. 
llvm-svn: 25860
 2006-02-01 00:15:53 +00:00
Evan Cheng 5659ca8f47 Be smarter about whether to store the SSE return value in memory. If 
it is already available in memory, do a fld directly from there.

llvm-svn: 25859
 2006-01-31 23:19:54 +00:00
Chris Lattner 64387c3e9c turning these into 'adds' would require extra copies 
llvm-svn: 25858
 2006-01-31 22:59:46 +00:00
Evan Cheng 72d5c256c9 - Allow XMM load (for scalar use) to be folded into ANDP* and XORP*. 
- Use XORP* to implement fneg.

llvm-svn: 25857
 2006-01-31 22:28:30 +00:00
Evan Cheng a91eb48547 Remove entries on fabs and fneg. These are done. 
llvm-svn: 25856
 2006-01-31 22:26:21 +00:00
Evan Cheng 32be2dc0af Allow the specification of explicit alignments for constant pool entries. 
llvm-svn: 25855
 2006-01-31 22:23:14 +00:00
Chris Lattner c642aa5e1c * Fix 80-column violations 
* Rename hasSSE -> hasSSE1 to avoid my continual confusion with 'has any SSE'.
* Add inline asm constraint specification.

llvm-svn: 25854
 2006-01-31 19:43:35 +00:00
Chris Lattner 0151361d21 add info about the inline asm register constraints for PPC 
llvm-svn: 25853
 2006-01-31 19:20:21 +00:00
Chris Lattner 0962ffc4a6 add a missing break that caused a lot of failures last night :( 
llvm-svn: 25851
 2006-01-31 17:20:06 +00:00
Nate Begeman a162f208ee Codegen 
bool %test(int %X) {
  %Y = seteq int %X, 13
  ret bool %Y
}

as

_test:
        addi r2, r3, -13
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

rather than

_test:
        cmpwi cr7, r3, 13
        mfcr r2
        rlwinm r3, r2, 31, 31, 31
        blr

This has very little effect on most code, but speeds up analyzer 23% and
mason 11%

llvm-svn: 25848
 2006-01-31 08:17:29 +00:00
Chris Lattner ac9892ccaf okay, one more 
llvm-svn: 25847
 2006-01-31 07:45:45 +00:00
Chris Lattner 882611dc25 another note 
llvm-svn: 25846
 2006-01-31 07:45:08 +00:00
Chris Lattner 24b0742476 More notes 
llvm-svn: 25845
 2006-01-31 07:43:33 +00:00
Chris Lattner 57480d0634 another one 
llvm-svn: 25844
 2006-01-31 07:38:32 +00:00
Chris Lattner 17cd988419 add a note 
llvm-svn: 25843
 2006-01-31 07:37:20 +00:00
Chris Lattner 799716141b add conditional moves of float and double values on int/fp condition codes. 
llvm-svn: 25842
 2006-01-31 07:26:55 +00:00
Chris Lattner b0fe138b65 example nate pointed out 
llvm-svn: 25841
 2006-01-31 07:16:34 +00:00
Chris Lattner 6f9bf658a7 treat conditional branches the same way as conditional moves (giving them 
an operand that contains the condcode), making things significantly simpler.

llvm-svn: 25840
 2006-01-31 06:56:30 +00:00
Chris Lattner 21ec192419 compactify all of the integer conditional moves into one instruction that takes 
a CC as an operand.  Much smaller, much happier.

llvm-svn: 25839
 2006-01-31 06:49:09 +00:00
Chris Lattner 196d58373c Add immediate forms of integer cmovs 
llvm-svn: 25838
 2006-01-31 06:24:29 +00:00
Chris Lattner 283492b4fe Shrinkify 
llvm-svn: 25837
 2006-01-31 06:18:16 +00:00
Chris Lattner 70c9e42593 Add the full complement of conditional moves of integer registers. 
llvm-svn: 25834
 2006-01-31 05:26:36 +00:00
Chris Lattner b6493b3165 Compile this: 
void %X(int %A) {
        %C = setlt int %A, 123          ; <bool> [#uses=1]
        br bool %C, label %T, label %F

T:              ; preds = %0
        call int %main( int 0 )         ; <int>:0 [#uses=0]
        ret void

F:              ; preds = %0
        ret void
}

to this:

X:
        save -96, %o6, %o6
        subcc %i0, 122, %l0
        bg .LBBX_2      ! F
        nop
...

not this:

X:
        save -96, %o6, %o6
        sethi 0, %l0
        or %g0, 1, %l1
        subcc %i0, 122, %l2
        bg .LBBX_4      !
        nop
.LBBX_3:        !
        or %g0, %l0, %l1
.LBBX_4:        !
        subcc %l1, 0, %l0
        bne .LBBX_2     ! F
        nop

llvm-svn: 25833
 2006-01-31 05:05:52 +00:00
Evan Cheng 2dd217b88f Added custom lowering of fabs 
llvm-svn: 25831
 2006-01-31 03:14:29 +00:00
Chris Lattner a9bfca8d1e add the 'lucas' optimization 
llvm-svn: 25830
 2006-01-31 02:55:28 +00:00
Chris Lattner 0e70729e83 I don't see why this optimization isn't safe, but it isn't, so disable it 
llvm-svn: 25829
 2006-01-31 02:45:52 +00:00
Chris Lattner d916e78b0a Another high-prio selection performance bug 
llvm-svn: 25828
 2006-01-31 02:10:06 +00:00
Chris Lattner 2b70a6f853 more mumbling 
llvm-svn: 25826
 2006-01-31 00:45:37 +00:00
Chris Lattner b521361fb9 add some notes 
llvm-svn: 25825
 2006-01-31 00:20:38 +00:00
Evan Cheng 45df7f84ff Don't generate complex sequence for SETOLE, SETOLT, SETULT, and SETUGT. Flip 
the order of the compare operands and generate SETOGT, SETOGE, SETUGE, and
SETULE instead.

llvm-svn: 25824
 2006-01-30 23:41:35 +00:00
Chris Lattner 9a90572374 Fix FP constants, and the SparcV8/2006-01-22-BitConvertLegalize.ll failure from last night 
llvm-svn: 25819
 2006-01-30 22:20:49 +00:00
Evan Cheng 08390f6a21 i64 -> f32, f32 -> i64 and some clean up. 
llvm-svn: 25818
 2006-01-30 22:13:22 +00:00
Evan Cheng 5b97fcf0f5 Always use FP stack instructions to perform i64 to f64 as well as f64 to i64 
conversions. SSE does not have instructions to handle these tasks.

llvm-svn: 25817
 2006-01-30 08:02:57 +00:00
Chris Lattner 37faeb2b02 Revamp the ICC/FCC reading instructions to be parameterized in terms of the 
SPARC condition codes, not in terms of the DAG condcodes.  This allows us to
write nice clean patterns for cmovs/branches.

llvm-svn: 25815
 2006-01-30 07:43:04 +00:00
Chris Lattner 33a79cae7c Compile: 
uint %test(uint %X) {
        %Y = call uint %llvm.ctpop.i32(uint %X)
        ret uint %Y
}

to:

test:
        save -96, %o6, %o6
        sll %i0, 0, %l0
        popc %l0, %i0
        restore %g0, %g0, %g0
        retl
        nop

instead of to 40 logical ops.  Note the shift-by-zero that clears the top
part of the 64-bit V9 register.

Testcase here: CodeGen/SparcV8/ctpop.ll

llvm-svn: 25814
 2006-01-30 06:14:02 +00:00
Chris Lattner 321e337d95 If the target has V9 instructions, this pass is a noop, don't bother 
running it.

llvm-svn: 25811
 2006-01-30 05:51:14 +00:00
Chris Lattner 90d3fd9e7c When in v9 mode, emit fabsd/fnegd/fmovd 
llvm-svn: 25810
 2006-01-30 05:48:37 +00:00