0a5314fdb3
Relocate with .bss instead of using the symbol. Matches gas behavior.
...
llvm-svn: 116741
2010-10-18 20:25:33 +00:00
f7a5e20372
Run tbaa before basicaa, since that's how it's expected to be used.
...
llvm-svn: 116731
2010-10-18 18:45:59 +00:00
e3dc9e2ea1
Produce ELF::R_386_GOTPC relocations.
...
llvm-svn: 116728
2010-10-18 18:36:12 +00:00
33fcde9b9c
Make TypeBasedAliasAnalysis default to doing nothing, with a command-line
...
option to enable it.
llvm-svn: 116722
2010-10-18 18:17:47 +00:00
02538ac4d3
Make BasicAliasAnalysis a normal AliasAnalysis implementation which
...
does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.
Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.
Update tests to explicitly request -basicaa.
llvm-svn: 116720
2010-10-18 18:04:47 +00:00
b9783dd9bc
Added a handful of x86-32 instructions that were missing so that llvm-mc would
...
be more complete. These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files. Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added. Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records. More missing instructions will be coming.
llvm-svn: 116716
2010-10-18 17:04:36 +00:00
3521f8467d
Produce a R_386_PLT32 when needed. Moved the default cases of switches to the
...
start for consistency.
llvm-svn: 116715
2010-10-18 16:58:03 +00:00
4464e0858f
Handle GOTOFF correctly on i386.
...
llvm-svn: 116711
2010-10-18 16:38:04 +00:00
5f2034c455
Improve lowering of sext to i128 on SPU.
...
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.
llvm-svn: 116701
2010-10-18 09:34:19 +00:00
4262a22225
Add a MCObjectFormat class so that code common to all targets that use a
...
single object format can be shared.
This also adds support for
mov zed+(bar-foo), %eax
on ELF and COFF targets.
llvm-svn: 116675
2010-10-16 18:23:53 +00:00
0d14b5b0fa
Unbreak test on non-COFF targets.
...
llvm-svn: 116669
2010-10-16 11:27:13 +00:00
17990d5690
MC-COFF: Add support for default-null weak externals.
...
llvm-svn: 116666
2010-10-16 08:25:57 +00:00
5e683250ee
X86-Windows: Emit an undefined global __fltused symbol when targeting Windows
...
if any floating point arguments are passed to an external function.
llvm-svn: 116665
2010-10-16 08:25:41 +00:00
18e4fed3fa
Generalize MemCpyOpt's handling of call slot forwarding to function properly when the call slot
...
forwarding is implemented with a load/store pair rather than a memcpy.
llvm-svn: 116637
2010-10-15 22:52:12 +00:00
3ba051a4f6
llvmc: Add a test for the -c flag.
...
llvm-svn: 116611
2010-10-15 19:30:49 +00:00
68a335e185
ARM mode encoding information for UBFX and SBFX instructions.
...
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
f28cc03802
FileCheckize
...
llvm-svn: 116581
2010-10-15 16:06:42 +00:00
fbcf0db7ee
Refactor code a bit and avoid creating unnecessary entries in the string
...
map.
llvm-svn: 116579
2010-10-15 15:39:06 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
0b5c743811
Simplify test file a bit.
...
llvm-svn: 116540
2010-10-14 23:32:44 +00:00
89efff3763
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
...
are just forms of that instruction).
llvm-svn: 116538
2010-10-14 23:29:18 +00:00
8b6a9c1574
Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos
...
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.
llvm-svn: 116534
2010-10-14 22:57:13 +00:00
062749cb25
Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx'
...
pseudonym.
llvm-svn: 116512
2010-10-14 20:43:44 +00:00
eafcb27ded
MOVi16 and MOVT ARM mode encodings.
...
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
bee6e9f8e0
Remove some code duplication.
...
llvm-svn: 116484
2010-10-14 16:34:44 +00:00
793d141b7d
Comments.
...
llvm-svn: 116476
2010-10-14 13:43:20 +00:00
6f52f8a87d
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
...
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
llvm-svn: 116471
2010-10-14 02:33:26 +00:00
0441c6cba0
Add encoding for 'fmstat'.
...
llvm-svn: 116466
2010-10-14 01:19:34 +00:00
0825f3e441
- Add encodings for multiply add/subtract instructions in all their glory.
...
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
llvm-svn: 116464
2010-10-14 01:02:08 +00:00
b9681ad442
fix a bug I introduced, no idea how this didn't repro right.
...
llvm-svn: 116462
2010-10-14 00:30:00 +00:00
c7bd5740eb
hack to unbreak buildbots
...
llvm-svn: 116461
2010-10-14 00:26:10 +00:00
698661c741
add uadd_ov/usub_ov to apint, consolidate constant folding
...
logic to use the new APInt methods. Among other things this
implements rdar://8501501 - llvm.smul.with.overflow.i32 should constant fold
which comes from "clang -ftrapv", originally brought to my attention from PR8221.
llvm-svn: 116457
2010-10-14 00:05:07 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
f106ecfa59
Add MC encodings for VCVT* instrunctions.
...
llvm-svn: 116431
2010-10-13 20:58:46 +00:00
1e7db68774
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
...
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
651dc7c9e9
Add ARM mode operand encoding information for ADDE/SUBE instructions.
...
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
2216af3fa8
Fix another case where we were preferring instructions with large
...
immediates instead of 8 bits ones.
llvm-svn: 116410
2010-10-13 17:14:25 +00:00
8ea9b0eb32
Fix PR8365 by adding a more specialized Pat that checks if an 'and' with
...
8 bit constants can be used.
llvm-svn: 116403
2010-10-13 13:31:20 +00:00
6e27b4f530
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
...
just yet.
llvm-svn: 116386
2010-10-13 01:17:33 +00:00
576fd0b110
Add encodings for VCVT instructions.
...
llvm-svn: 116385
2010-10-13 00:56:35 +00:00
8c519c0d4b
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
...
arithmetic-with-carry-in instructions.
llvm-svn: 116384
2010-10-13 00:50:27 +00:00
da4ddf0fcf
Add VCMPZ and VABS.
...
llvm-svn: 116383
2010-10-13 00:38:07 +00:00
f9ca535495
Refactor VCMP instructions.
...
llvm-svn: 116379
2010-10-13 00:04:29 +00:00
a237bdbe52
FileCheckize this in a hope to quiet a valgrind warning on grep.
...
llvm-svn: 116376
2010-10-12 23:47:58 +00:00
7dd8c0b991
Add encodings for VNMUL[SD].
...
llvm-svn: 116375
2010-10-12 23:47:37 +00:00
a06aee826c
Add encodings for VDIV and VMUL.
...
llvm-svn: 116370
2010-10-12 23:22:27 +00:00
d5f8c3350d
Be nitpicky and line up the comments.
...
llvm-svn: 116365
2010-10-12 23:14:03 +00:00
646a506724
Add encoding for VSUB and VCMP.
...
Fear not! I'm going to try a refactoring right now. :)
llvm-svn: 116359
2010-10-12 22:55:35 +00:00
9513a7e87f
Don't need to specify calling convention. Add 'readnone' to functions.
...
llvm-svn: 116354
2010-10-12 22:24:10 +00:00
ac6cd00706
Encoding for VADDD. Plus a test for the VFP instructions.
...
llvm-svn: 116348
2010-10-12 22:08:41 +00:00
Rafael Espindola