e67b77028e
Add explicit types for shift count constants. This is in preparation for
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another change that makes the types ambiguous (at least as far as tablegen
is concerned).
llvm-svn: 73909
2009-06-22 22:08:29 +00:00
482495695e
Use thumb2 for ARM architectures V6T2 and later. Fix a bug in checking
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for "thumb" and add a check for V6T2.
llvm-svn: 73905
2009-06-22 21:28:22 +00:00
4582530a2c
For Darwin on ARMv6 and newer, make register r9 available for use as a
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caller-saved register.
llvm-svn: 73901
2009-06-22 21:01:46 +00:00
3d75d6af57
hasFP should return true if frame address is taken.
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llvm-svn: 73893
2009-06-22 18:38:48 +00:00
360eef0782
Fix llvm-gcc build for armv6t2 and later architectures. The hasV6T2Ops
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predicate does not check if Thumb mode is enabled, and when in ARM mode
there are still some checks for constant-pool use that need to run.
llvm-svn: 73887
2009-06-22 17:29:13 +00:00
79ef65a271
Remove unused field.
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llvm-svn: 73815
2009-06-20 01:07:54 +00:00
b4b20bbb7d
Enable arm pre-allocation load / store multiple optimization pass.
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llvm-svn: 73791
2009-06-19 23:17:27 +00:00
33f4eb462f
Move up dwarf writer initialization in common AsmPrinter class.
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llvm-svn: 73784
2009-06-19 21:54:26 +00:00
d305869ca2
Add comments.
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llvm-svn: 73761
2009-06-19 07:06:07 +00:00
1592035e67
Should be using Bcc (average) latency to determine if-conversion threshold, not BL.
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llvm-svn: 73759
2009-06-19 06:56:26 +00:00
5d8df7ff34
Transfer dead markers when a ldrd is changed into a ldm or a pair of ldr.
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llvm-svn: 73749
2009-06-19 01:59:04 +00:00
4e712de541
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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llvm-svn: 73747
2009-06-19 01:51:50 +00:00
d984158320
Mark a few Thumb instructions commutable; just happened to spot this
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while experimenting. I'm reasonably sure this is correct, but please
tell me if these instructions have some strange property which makes this
change unsafe.
llvm-svn: 73746
2009-06-19 01:43:08 +00:00
8284b66264
merge the common darwin settings from the X86/PPC/ARM targets
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into DarwinTargetAsmInfo.cpp. The remaining differences should
be evaluated. It seems strange that x86/arm has .zerofill but ppc
doesn't, etc.
llvm-svn: 73742
2009-06-19 00:08:39 +00:00
b84764516d
move mangler quote handling from asm printers to TargetAsmInfo.
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llvm-svn: 73738
2009-06-18 23:41:35 +00:00
09081b25a5
simplify macro debug info directive handling.
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llvm-svn: 73736
2009-06-18 23:31:37 +00:00
a0ca298f8a
Remove UseThumbBacktraces. Just check if subtarget is darwin.
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llvm-svn: 73734
2009-06-18 23:14:30 +00:00
de9e36a74e
On Darwin, ams printer should output a second label before a jump table so the linker knows it's a new atom. But this is only needed if the jump table is put in a separate section from the function body.
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llvm-svn: 73720
2009-06-18 20:37:15 +00:00
0e79603588
- Update register allocation hint after coalescing. This is done by the target since the hint is target dependent. This is important for ARM register pair hints.
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- Register allocator should resolve the second part of the hint (register number) before passing it to the target since it knows virtual register to physical register mapping.
- More fixes to get ARM load / store double word working.
llvm-svn: 73671
2009-06-18 02:04:01 +00:00
86c12d7bc4
ARM unified syntax is not specific to ELF; use it for Darwin, too.
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llvm-svn: 73665
2009-06-18 00:36:17 +00:00
5658086052
Fix asm string from MOVi16
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llvm-svn: 73661
2009-06-17 23:43:36 +00:00
f687a828b2
Thumb2 instructions are enabled only in unified assembler mode.
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Emit switch directive for it. I have no idea whether this is
requirement for Darwin or not.
llvm-svn: 73660
2009-06-17 23:43:18 +00:00
02bb33c58d
Initial support for some Thumb2 instructions.
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Patch by Viktor Kutuzov and Anton Korzh from Access Softek, Inc.
llvm-svn: 73622
2009-06-17 18:13:58 +00:00
1b731d5dbe
Introduce new headers whose inclusion forces linking and
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initialization of all targets (InitializeAllTargets.h) or assembler
printers (InitializeAllAsmPrinters.h). This is a step toward the
elimination of relinked object files, so that we can build normal
archives.
llvm-svn: 73543
2009-06-16 20:12:29 +00:00
a8fd40b50a
Address review comments: add 3 ARM calling conventions.
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Dispatch C calling conv. to one of these conventions based on
target triple and subtarget features.
llvm-svn: 73530
2009-06-16 18:50:49 +00:00
5d28cb204f
GNU as refuses to assemble "pop {}" instruction. Do not emit such
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(this is the case when we have thumb vararg function with single
callee-saved register, which is handled separately).
llvm-svn: 73529
2009-06-16 18:49:08 +00:00
f691b829ab
On Darwin, frame pointer r7 is never available.
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llvm-svn: 73434
2009-06-15 22:32:01 +00:00
409105fc95
Rename methods for the sake of consistency.
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llvm-svn: 73428
2009-06-15 21:46:20 +00:00
ad0dba582f
Typo.
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llvm-svn: 73422
2009-06-15 21:18:20 +00:00
eba57e41b3
Do not form ldrd / strd if the two dests / srcs are the same. Code clean up.
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llvm-svn: 73413
2009-06-15 20:54:56 +00:00
1cf0f193b0
Silence a warning.
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llvm-svn: 73406
2009-06-15 19:36:32 +00:00
1283c6a066
Part 1.
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- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
2009-06-15 08:28:29 +00:00
185c9ef0a2
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
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consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
llvm-svn: 73291
2009-06-13 09:12:55 +00:00
d93b5b672f
Mark some pattern-less instructions as neverHasSideEffects.
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llvm-svn: 73252
2009-06-12 20:46:18 +00:00
5b1b5b2a8a
Typo
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llvm-svn: 73098
2009-06-08 22:59:50 +00:00
3708883bfe
Revert hunk commited by accident
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llvm-svn: 73097
2009-06-08 22:57:18 +00:00
77d1943637
The attached patches implement most of the ARM AAPCS-VFP hard float
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ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
llvm-svn: 73095
2009-06-08 22:53:56 +00:00
c82b282b34
Separate V6 from V6T2 since the latter has some extra nice instructions
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llvm-svn: 73085
2009-06-08 21:20:36 +00:00
cd41a9019e
Add helper for checking of Thumb1 mode
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llvm-svn: 73080
2009-06-08 20:31:02 +00:00
d185a7a629
Add explicit keywords.
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llvm-svn: 72969
2009-06-05 23:05:51 +00:00
3158790e32
Changing allocation ordering from r3 ... r0 back to r0 ... r3. The order change no longer make sense after the coalescing changes we have made since then.
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llvm-svn: 72955
2009-06-05 19:08:58 +00:00
7fce2cf0ba
When merging multiple load / store instructions. Use the DebugLoc of the first one.
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llvm-svn: 72952
2009-06-05 18:19:23 +00:00
c154c1185c
Code clean up: return vector by reference rather than by value. No functionality changes.
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llvm-svn: 72950
2009-06-05 17:56:14 +00:00
d9ef48a73e
Remove some unnecessary #includes.
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llvm-svn: 72948
2009-06-05 16:32:58 +00:00
7f5976e11b
Re-apply 72756 with fixes. One of those was introduced by we changed MachineInstrBuilder::addReg() interface.
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llvm-svn: 72826
2009-06-04 01:15:28 +00:00
ab0c710fae
Temporarily revert 72756 for now.
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llvm-svn: 72757
2009-06-03 07:40:47 +00:00
dfe6e689fd
Fold preceding / trailing base inc / dec into the single load / store as well.
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llvm-svn: 72756
2009-06-03 06:14:58 +00:00
12694bd8ac
Implement review feedback. Make thumb2 'normal' subtarget feature
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llvm-svn: 72698
2009-06-01 20:00:48 +00:00
9fd794bebf
Fix new CodeEmitter stuff to follow LLVM codying style. Patch by Aaron Gray
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llvm-svn: 72697
2009-06-01 19:57:37 +00:00
2afc641e04
Do not emit "generic" CPU string. This fixes PR4291.
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llvm-svn: 72696
2009-06-01 19:03:17 +00:00
Bob Wilson