Commit Graph

89 Commits

Author SHA1 Message Date
Evan Cheng 12134701ec Revert 56176. All those instruction formats are still needed.
llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng c5c74f36fd Eliminate unnecessary instruction formats.
llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng 33fa89c6fb Rewrite address mode 1 code emission routines.
llvm-svn: 56171
2008-09-12 22:01:15 +00:00
Owen Anderson 27fb3dcbc7 Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy requested
was inserted or not.  This allows bitcast in fast isel to properly handle the case
where an appropriate reg-to-reg copy is not available.

llvm-svn: 55375
2008-08-26 18:03:31 +00:00
Owen Anderson 4f6bf04616 Convert uses of std::vector in TargetInstrInfo to SmallVector. This change had to be propoagated down into all the targets and up into all clients of this API.
llvm-svn: 54802
2008-08-14 22:49:33 +00:00
Owen Anderson 30cc028e4a Make LiveVariables even more optional, by making it optional in the call to TargetInstrInfo::convertToThreeAddressInstruction
Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place.

llvm-svn: 53058
2008-07-02 23:41:07 +00:00
Dan Gohman eabd647cd5 Change target-specific classes to use more precise static types.
This eliminates the need for several awkward casts, including
the last dynamic_cast under lib/Target.

llvm-svn: 51091
2008-05-14 01:58:56 +00:00
Nicolas Geoffray ae84bbdbed Infrastructure for getting the machine code size of a function and an instruction. X86, PowerPC and ARM are implemented
llvm-svn: 49809
2008-04-16 20:10:13 +00:00
Evan Cheng ed6e34fe41 Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.
llvm-svn: 48995
2008-03-31 20:40:39 +00:00
Dan Gohman c60c67fc37 Add explicit keywords.
llvm-svn: 48801
2008-03-25 22:06:05 +00:00
Dan Gohman 3a4be0fdef Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
2008-02-10 18:45:23 +00:00
Evan Cheng 3b3286d4bc It's not always safe to fold movsd into xorpd, etc. Check the alignment of the load address first to make sure it's 16 byte aligned.
llvm-svn: 46893
2008-02-08 21:20:40 +00:00
Owen Anderson 2a3be7bb6c Move even more functionality from MRegisterInfo into TargetInstrInfo.
Some day I'll get it all moved over...

llvm-svn: 45672
2008-01-07 01:35:02 +00:00
Owen Anderson 6bb0c52628 Move some more functionality from MRegisterInfo to TargetInstrInfo.
llvm-svn: 45603
2008-01-04 23:57:37 +00:00
Owen Anderson eee14601b1 Move some more instruction creation methods from RegisterInfo into InstrInfo.
llvm-svn: 45484
2008-01-01 21:11:32 +00:00
Chris Lattner 25568e4cef Fix a problem where lib/Target/TargetInstrInfo.h would include and use
a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to 
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where 
the base is not.

llvm-svn: 45475
2008-01-01 01:03:04 +00:00
Owen Anderson 7a73ae9a86 Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the
Machine-level API cleanup instigated by Chris.

llvm-svn: 45470
2007-12-31 06:32:00 +00:00
Chris Lattner f3ebc3f3d2 Remove attribution from file headers, per discussion on llvmdev.
llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Christopher Lamb 79dfbed6f6 Fix a misnamed parameter.
llvm-svn: 43145
2007-10-18 19:29:45 +00:00
Raul Herbster ab871baaf8 Instruction formats added used to generate multiply instructions of V5TE.
llvm-svn: 41629
2007-08-30 23:34:14 +00:00
Evan Cheng f7c6effc44 Initial JIT support for ARM by Raul Fernandes Herbster.
llvm-svn: 40887
2007-08-07 01:37:15 +00:00
Evan Cheng 9d41b311fb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit.
llvm-svn: 38501
2007-07-10 18:08:01 +00:00
Dan Gohman e8c1e428f2 Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman 9e82064924 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng a7ca624028 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37643
2007-06-19 01:26:51 +00:00
Evan Cheng 36b1f5476e Instructions with unique labels or embedded jumptables cannot be duplicated during ifcvt.
llvm-svn: 37606
2007-06-15 21:15:00 +00:00
Evan Cheng 2d91a4fd6a Add missing const qualifiers.
llvm-svn: 37342
2007-05-29 18:42:18 +00:00
Evan Cheng 1d764eca98 Hooks for predication support.
llvm-svn: 37308
2007-05-23 07:22:05 +00:00
Evan Cheng e20dd92792 RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
llvm-svn: 37193
2007-05-18 00:18:17 +00:00
Evan Cheng dcff2eb0e8 PredicateInstruction returns true if the operation was successful.
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
Evan Cheng e2762c3d68 Removed isPredicable().
llvm-svn: 37119
2007-05-16 20:50:23 +00:00
Evan Cheng ad3aac71ce Hooks for predication support.
llvm-svn: 37093
2007-05-16 02:01:49 +00:00
Evan Cheng 760c68b8af Factor GetInstSize() out of constpool island pass.
llvm-svn: 33644
2007-01-29 23:45:17 +00:00
Jim Laskey f9e5445ed4 Make LABEL a builtin opcode.
llvm-svn: 33537
2007-01-26 14:34:52 +00:00
Evan Cheng 10043e215b ARM backend contribution from Apple.
llvm-svn: 33353
2007-01-19 07:51:42 +00:00
Chris Lattner aaeede0aa2 implement uncond branch insertion, mark branches with isBranch.
llvm-svn: 31160
2006-10-24 16:47:57 +00:00
Rafael Espindola 8c41f99e6f change the addressing mode of the str instruction to reg+imm
llvm-svn: 29571
2006-08-08 20:35:03 +00:00
Rafael Espindola e40a7e2aa2 create the raddr addressing mode that matches any register and the frame index
use raddr for the ldr instruction. This removes a dummy mov from the assembly output
remove SelectFrameIndex
remove isLoadFromStackSlot
remove isStoreToStackSlot

llvm-svn: 29079
2006-07-10 01:41:35 +00:00
Rafael Espindola ffdc24b847 added a skeleton of the ARM backend
llvm-svn: 28301
2006-05-14 22:18:28 +00:00