Commit Graph

1370 Commits

Author SHA1 Message Date
Ron Lieberman 88159e5549 Make sure to maintain register liveness when generating predicated instructions.
Author: Krzysztof Parzyszek <kparzysz@codeaurora.org>

Differential Revision: https://reviews.llvm.org/D24209

llvm-svn: 280552
2016-09-02 22:56:24 +00:00
Krzysztof Parzyszek 07d9f53b51 [Hexagon] Deal with undefs when extending live intervals
Reapply r280275, since MSVC accepts r280358.

llvm-svn: 280369
2016-09-01 13:59:35 +00:00
Dean Michael Berris 6d6addbe15 [NFC] Remove unnecessary comment
llvm-svn: 280336
2016-09-01 01:58:24 +00:00
Dean Michael Berris 40e6ba16a1 [XRay][NFC] Promote isTailCall() as virtual in TargetInstrInfo.
This change is broken out from D23986, where XRay detects tail call
exits.

llvm-svn: 280331
2016-09-01 01:03:22 +00:00
Reid Kleckner 109448ee81 Revert "Add an optional parameter with a list of undefs to extendToIndices"
This reverts commit r280268, it causes all MSVC 2013 to ICE. This
appears to have been fixed in a later MSVC 2013 update, because I cannot
reproduce it locally. That said, all upstream LLVM bots are broken right
now, so I am reverting.

Also reverts dependent change r280275, "[Hexagon] Deal with undefs when
extending live intervals".

llvm-svn: 280301
2016-08-31 22:36:02 +00:00
Krzysztof Parzyszek e21a0b3b9f [Hexagon] Deal with undefs when extending live intervals
llvm-svn: 280275
2016-08-31 18:52:09 +00:00
Ron Lieberman a3c739b977 [Hexagon] Remove extraneous debug output from HexagonCopyToCombine.cpp
BB# ...

llvm-svn: 279750
2016-08-25 16:46:09 +00:00
Ron Lieberman c93d123b86 [Hexagon] vector store print tracing.
Add vector store print tracing option for hexagon vector instructions.

https://reviews.llvm.org/D23870

llvm-svn: 279739
2016-08-25 13:35:48 +00:00
Matthias Braun 1eb473680a MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of
running after register and simply describes that no vregs are used in
a machine function. With that we can simply compute the property and do
not need to dump/parse it in .mir files.

Differential Revision: http://reviews.llvm.org/D23850

llvm-svn: 279698
2016-08-25 01:27:13 +00:00
Krzysztof Parzyszek 6dff336ad1 [Hexagon] Check for block end when skipping debug instructions
llvm-svn: 279681
2016-08-24 22:36:35 +00:00
Krzysztof Parzyszek 951fb36120 [Hexagon] Change insertion of expand-condsets pass to avoid memory leaks
llvm-svn: 279678
2016-08-24 22:27:36 +00:00
Krzysztof Parzyszek b5ec48755d [Hexagon] Enable subregister liveness tracking
llvm-svn: 279642
2016-08-24 17:17:39 +00:00
Krzysztof Parzyszek cbd559f507 [Hexagon] Remove the utilization of IMPLICIT_DEFs from expand-condsets
This is no longer necessary, because since r279625 the subregister
liveness properly accounts for read-undefs.

llvm-svn: 279637
2016-08-24 16:36:37 +00:00
Krzysztof Parzyszek a7ed090bba Create subranges for new intervals resulting from live interval splitting
The register allocator can split a live interval of a register into a set
of smaller intervals. After the allocation of registers is complete, the
rewriter will modify the IR to replace virtual registers with the corres-
ponding physical registers. At this stage, if a register corresponding
to a subregister of a virtual register is used, the rewriter will check
if that subregister is undefined, and if so, it will add the <undef> flag
to the machine operand. The function verifying liveness of the subregis-
ter would assume that it is undefined, unless any of the subranges of the
live interval proves otherwise.
The problem is that the live intervals created during splitting do not
have any subranges, even if the original parent interval did. This could
result in the <undef> flag placed on a register that is actually defined.

Differential Revision: http://reviews.llvm.org/D21189

llvm-svn: 279625
2016-08-24 13:37:55 +00:00
Matthias Braun 733fe3676c CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
Re-apply this patch, hopefully I will get away without any warnings
in the constructor now.

This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.

This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.

Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.

Differential Revision: http://reviews.llvm.org/D23736

llvm-svn: 279602
2016-08-24 01:52:46 +00:00
Richard Smith 8c3fbdc6c4 Revert r279564. It introduces undefined behavior (binding a reference to a
dereferenced null pointer) in MachineModuleInfo::MachineModuleInfo that causes
-Werror builds (including several buildbots) to fail.

llvm-svn: 279580
2016-08-23 22:08:27 +00:00
Matthias Braun 4c1f1f120c CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
Re-apply this commit with the deletion of a MachineFunction delegated to
a separate pass to avoid use after free when doing this directly in
AsmPrinter.

This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.

This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.

Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.

Differential Revision: http://reviews.llvm.org/D23736

llvm-svn: 279564
2016-08-23 20:58:29 +00:00
Krzysztof Parzyszek 38e2ccc8d0 [Hexagon] Packetize return value setup with the return instruction
Commit r279241 unintentionally reverted that ability.

llvm-svn: 279526
2016-08-23 16:01:01 +00:00
Matthias Braun 7f66202d38 Revert "(HEAD -> master, origin/master, origin/HEAD) CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses"
Reverting while tracking down a use after free.

This reverts commit r279502.

llvm-svn: 279503
2016-08-23 05:17:11 +00:00
Matthias Braun fd936841eb CodeGen: Remove MachineFunctionAnalysis => Enable (Machine)ModulePasses
This patch removes the MachineFunctionAnalysis. Instead we keep a
map from IR Function to MachineFunction in the MachineModuleInfo.

This allows the insertion of ModulePasses into the codegen pipeline
without breaking it because the MachineFunctionAnalysis gets dropped
before a module pass.

Peak memory should stay unchanged without a ModulePass in the codegen
pipeline: Previously the MachineFunction was freed at the end of a codegen
function pipeline because the MachineFunctionAnalysis was dropped; With
this patch the MachineFunction is freed after the AsmPrinter has
finished.

Differential Revision: http://reviews.llvm.org/D23736

llvm-svn: 279502
2016-08-23 03:20:09 +00:00
Krzysztof Parzyszek 29a6a2eb8f [Hexagon] Avoid register dependencies on indirect branches in packetizer
Do not packetize the instruction setting the branch address with the
indirect branch itself.

llvm-svn: 279324
2016-08-19 21:07:35 +00:00
Krzysztof Parzyszek fb4c4178a2 [Hexagon] Fix subesthetic indentation
llvm-svn: 279303
2016-08-19 19:29:15 +00:00
Krzysztof Parzyszek 505eb498bd [Hexagon] Allow i1 values for 'r' constraint in inline-asm
llvm-svn: 279302
2016-08-19 19:17:28 +00:00
Krzysztof Parzyszek 8849a51370 [Hexagon] Do not cache alloca instructions during isel
They can be deleted or replicated, so the cache may become outdated.
They only need to be visited once during frame lowering, so just scan
the function instead.

llvm-svn: 279297
2016-08-19 18:46:13 +00:00
Krzysztof Parzyszek 3d9946eb23 [Hexagon] Fixes for new-value jump formation
- Recognize C2_cmpgtui, S2_tstbit_i, and S4_ntstbit_i.
- Avoid creating new-value instructions with both source operands equal.

llvm-svn: 279286
2016-08-19 17:54:49 +00:00
Krzysztof Parzyszek 5a7bef9c14 [Hexagon] Fix a few omissions in HexagonInstrInfo
llvm-svn: 279280
2016-08-19 17:20:57 +00:00
Krzysztof Parzyszek 639545b4d8 [Hexagon] Enforce LLSC packetization rules
Ensure that load locked and store conditional instructions are only
packetized with ALU32 instructions.

Patch by Ben Craig.

llvm-svn: 279272
2016-08-19 16:57:05 +00:00
Krzysztof Parzyszek b7640d4df0 [Hexagon] Minor updates to register definitions
llvm-svn: 279269
2016-08-19 16:40:19 +00:00
Krzysztof Parzyszek 9335bf0ec5 [Hexagon] Fix incorrect generation of S4_subi_asl_ri
Patch by Jyotsna Verma.

llvm-svn: 279267
2016-08-19 16:35:05 +00:00
Krzysztof Parzyszek dddb097a1f [Hexagon] Add missing pattern for C4_cmplte
llvm-svn: 279265
2016-08-19 16:11:33 +00:00
Krzysztof Parzyszek 0b8672269c [Hexagon] Make p0 an explicit operand in VA1_clr* subinstructions, NFC
llvm-svn: 279255
2016-08-19 15:17:19 +00:00
Krzysztof Parzyszek 6ce82951c3 [Hexagon] Add explicit default constructor for HexagonSelectionDAGInfo
llvm-svn: 279254
2016-08-19 15:13:54 +00:00
Krzysztof Parzyszek 0ba9754584 [Hexagon] Allow tail-call optimization when mixing C and fast calling conv
Patch by Arnold Schwaighofer.

llvm-svn: 279251
2016-08-19 15:02:18 +00:00
Krzysztof Parzyszek 66dd6797e8 [Hexagon] Check for empty live interval
Patch by Brendon Cahoon.

llvm-svn: 279249
2016-08-19 14:29:43 +00:00
Krzysztof Parzyszek db019ae801 [Hexagon] Consider zext/sext of a load to i32 to be free
llvm-svn: 279248
2016-08-19 14:22:07 +00:00
Krzysztof Parzyszek a243adfd27 [Hexagon] Handle J2_jumptpt and J2_jumpfpt instructions
llvm-svn: 279246
2016-08-19 14:14:09 +00:00
Krzysztof Parzyszek 067debe0a0 [Hexagon] Fix indentation, NFC
llvm-svn: 279245
2016-08-19 14:12:51 +00:00
Krzysztof Parzyszek 9273ecc176 [Hexagon] Remove unnecessary llvm::, NFC
llvm-svn: 279244
2016-08-19 14:10:57 +00:00
Krzysztof Parzyszek 75e74ee699 [Hexagon] Rename the HEXAGON_MC namespace to Hexagon_MC, NFC
llvm-svn: 279243
2016-08-19 14:09:47 +00:00
Krzysztof Parzyszek 6421b934ec [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr
llvm-svn: 279241
2016-08-19 14:04:45 +00:00
Krzysztof Parzyszek bd8ef4b8ce [Hexagon] Improvements to handling and generation of FP instructions
Improved handling of fma, floating point min/max, additional load/store
instructions for floating point types.

Patch by Jyotsna Verma.

llvm-svn: 279239
2016-08-19 13:34:31 +00:00
Michael Kuperstein 2bc3d4d46c [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround
The names of the tablegen defs now match the names of the ISD nodes.
This makes the world a slightly saner place, as previously "fround" matched
ISD::FP_ROUND and not ISD::FROUND.

Differential Revision: https://reviews.llvm.org/D23597

llvm-svn: 279129
2016-08-18 20:08:15 +00:00
Krzysztof Parzyszek b1b0372337 [Hexagon] Create vcombine in HexagonCopyToCombine
llvm-svn: 279067
2016-08-18 14:12:34 +00:00
Justin Bogner cd1d5aaf2e Replace a few more "fall through" comments with LLVM_FALLTHROUGH
Follow up to r278902. I had missed "fall through", with a space.

llvm-svn: 278970
2016-08-17 20:30:52 +00:00
Justin Bogner b03fd12cef Replace "fallthrough" comments with LLVM_FALLTHROUGH
This is a mechanical change of comments in switches like fallthrough,
fall-through, or fall-thru to use the LLVM_FALLTHROUGH macro instead.

llvm-svn: 278902
2016-08-17 05:10:15 +00:00
Duncan P. N. Exon Smith e04fe1a394 Hexagon: Avoid dereferencing end() in HexagonInstrInfo::InsertBranch
llvm-svn: 278878
2016-08-17 00:34:00 +00:00
Krzysztof Parzyszek 1d01a79304 [Hexagon] Standardize next batch of pseudo instructions
ALIGNA          PS_aligna
ALLOCA          PS_alloca
TFR_FI          PS_fi
TFR_FIA         PS_fia
TFR_PdFalse     PS_false
TFR_PdTrue      PS_true
VMULW           PS_vmulw
VMULW_ACC       PS_vmulw_acc

llvm-svn: 278832
2016-08-16 18:08:40 +00:00
Krzysztof Parzyszek eabc0d0fd5 [Hexagon] Clean up some miscellaneous V60 intrinsics a bit
llvm-svn: 278823
2016-08-16 17:14:44 +00:00
Krzysztof Parzyszek 17aa4136a2 [Hexagon] Standardize vector predicate load/store pseudo instructions
- Remove unused instructions: LDriq_pred_vec_V6, STriq_pred_vec_V6, and
  the 128B counterparts.
- Rename:
    LDriq_pred_V6         PS_vloadrq_ai
    LDriq_pred_V6_128B    PS_vloadrq_ai_128B
    STriq_pred_V6         PS_vstorerq_ai
    STriq_pred_V6_128B    PS_vstorerq_ai_128B

llvm-svn: 278813
2016-08-16 15:43:54 +00:00
Sjoerd Meijer 58156715b4 MachineLoop: add methods findLoopControlBlock and findLoopPreheader
This adds two new utility functions findLoopControlBlock and findLoopPreheader
to MachineLoop and MachineLoopInfo. These functions are refactored and taken
from the Hexagon target as they are target independent; thus this is intendend to
be a non-functional change.

Differential Revision: https://reviews.llvm.org/D22959

llvm-svn: 278661
2016-08-15 08:22:42 +00:00