75169a82d6
Get X86 long double calling convention to work
...
(on Darwin, anyway). Fix some table omissions for
LD arithmetic.
llvm-svn: 40877
2007-08-06 21:31:06 +00:00
473c5111c3
Switch some multiplication instructions over to the new scheme for testing.
...
llvm-svn: 40723
2007-08-02 05:48:35 +00:00
763cdfd371
Mac OS X X86-64 low 4G address not available.
...
llvm-svn: 40701
2007-08-01 23:45:51 +00:00
5fecb80efa
Change the x86 backend to use extract_subreg for truncation operations. Passes DejaGnu, SingleSource and MultiSource.
...
llvm-svn: 40578
2007-07-29 01:24:57 +00:00
ca6e041903
Minor bug.
...
llvm-svn: 40535
2007-07-26 17:02:45 +00:00
ce5185b181
Same goes for constantpool, etc.
...
llvm-svn: 40517
2007-07-26 07:35:15 +00:00
630c1f75b8
Mac OS X x86-64 lower 4G address is not available.
...
llvm-svn: 40502
2007-07-25 23:41:36 +00:00
f0bb12848f
Add const to CanBeFoldedBy, CheckAndMask, and CheckOrMask.
...
llvm-svn: 40480
2007-07-24 23:00:27 +00:00
a2b3c175db
Fix for PR 1505 (and 1489). Rewrite X87 register
...
model to include f32 variants. Some factoring
improvments forthcoming.
llvm-svn: 37847
2007-07-03 00:53:03 +00:00
309d3d51b3
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
...
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
llvm-svn: 37704
2007-06-22 14:59:07 +00:00
a5fcd24746
Fix CodeGen/X86/2007-03-24-InlineAsmPModifier.ll
...
llvm-svn: 35926
2007-04-11 22:29:46 +00:00
0ad22563b8
Oops :)
...
llvm-svn: 35438
2007-03-28 18:38:33 +00:00
7522c9d8e1
Don't allow MatchAddress recurse too much. This trims exponential
...
behaviour in some cases.
llvm-svn: 35437
2007-03-28 18:36:33 +00:00
3e1d917e80
Two changes:
...
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
in three-address form.
This gives us asm diffs like:
- leal (,%eax,4), %eax
+ shll $2, %eax
which is faster on some processors and smaller on all of them.
and, more interestingly:
- movl 24(%esi), %eax
- leal (,%eax,4), %edi
+ movl 24(%esi), %edi
+ shll $2, %edi
Without #2 , #1 was a significant pessimization in some cases.
This implements CodeGen/X86/shift-codegen.ll
llvm-svn: 35204
2007-03-20 06:08:29 +00:00
fe8c530d79
Fix a miscompilation in the addr mode code trying to implement X | C and
...
X + C to promote LEA formation. We would incorrectly apply it in some cases
(test) and miss it in others.
This fixes CodeGen/X86/2007-02-04-OrAddrMode.ll
llvm-svn: 33884
2007-02-04 20:18:17 +00:00
1281dc32ef
Linux GOT indirect reference is only necessary in PIC mode.
...
llvm-svn: 33441
2007-01-22 21:34:25 +00:00
015b432b54
Adjust #includes to compensate for lost of DerivedTypes.h in
...
TargetLowering.h
llvm-svn: 33154
2007-01-12 23:22:14 +00:00
a0554d90e8
* PIC codegen for X86/Linux has been implemented
...
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
llvm-svn: 33136
2007-01-12 19:20:47 +00:00
4efbbc963f
Really big cleanup.
...
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
llvm-svn: 32833
2007-01-03 11:43:14 +00:00
1ef9cd400d
eliminate static ctors for Statistic objects.
...
llvm-svn: 32703
2006-12-19 22:59:26 +00:00
582ac4bed7
Fix for PR1062 by Dan Gohman.
...
llvm-svn: 32688
2006-12-19 21:31:42 +00:00
9bfb1e1f29
What should be the last unnecessary <iostream>s in the library.
...
llvm-svn: 32333
2006-12-07 22:21:48 +00:00
700b873130
Detemplatize the Statistic class. The only type it is instantiated with
...
is 'unsigned'.
llvm-svn: 32279
2006-12-06 17:46:33 +00:00
47e181cc4d
Revert an unintended change.
...
llvm-svn: 32239
2006-12-05 22:03:40 +00:00
dd60ca029c
- Switch X86-64 JIT to large code size model.
...
- Re-enable some codegen niceties for X86-64 static relocation model codegen.
- Clean ups, etc.
llvm-svn: 32238
2006-12-05 19:50:18 +00:00
62cdc3f011
- Fix X86-64 JIT by temporarily disabling code that treats GV address as 32-bit
...
immediate in small code model. The JIT cannot ensure GV's are placed in the
lower 4G.
- Some preliminary support for large code model.
llvm-svn: 32215
2006-12-05 04:01:03 +00:00
ae1cd75af7
- Use a different wrapper node for RIP-relative GV, etc.
...
- Proper support for both small static and PIC modes under X86-64
- Some (non-optimal) support for medium modes.
llvm-svn: 32046
2006-11-30 21:55:46 +00:00
8c84c7cd0d
Clean up.
...
llvm-svn: 32027
2006-11-29 23:46:27 +00:00
0b1692216d
Fix for PR1018 - Better support for X86-64 Linux in small code model.
...
llvm-svn: 32026
2006-11-29 23:19:46 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
...
of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
9e8093ae20
For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX while
...
clearing the upper 8-bits instead of issuing two instructions. This also
eliminates the need to target the AH register which can be problematic on
x86-64.
llvm-svn: 31832
2006-11-17 22:10:14 +00:00
c8e81b8d48
Removed even more std::cerr and #include <iostream> things.
...
llvm-svn: 31813
2006-11-17 07:52:03 +00:00
dbd3d294e6
Matches MachineInstr changes.
...
llvm-svn: 31712
2006-11-13 23:36:35 +00:00
db04c958a5
Add implicit use / def operands to created MI's.
...
llvm-svn: 31676
2006-11-11 10:21:44 +00:00
a36cdcfaf8
Add all implicit defs to FP_REG_KILL mi.
...
llvm-svn: 31674
2006-11-11 07:19:36 +00:00
fb44822a98
Fix a bug in SelectScalarSSELoad. Since the load is wrapped in a
...
SCALAR_TO_VECTOR, even if the hasOneUse() check pass we may end up folding
the load into two instructions. Make sure we check the SCALAR_TO_VECTOR
has only one use as well.
llvm-svn: 31641
2006-11-10 21:23:04 +00:00
6cd0909da7
Match tblegen changes.
...
llvm-svn: 31571
2006-11-08 20:34:28 +00:00
7d6f3db3e2
Unbreak VC++ build.
...
llvm-svn: 31464
2006-11-05 19:31:28 +00:00
de2f0906e4
silence warning
...
llvm-svn: 31393
2006-11-03 01:13:15 +00:00
ff1a712794
SelectScalarSSELoad should call CanBeFoldedBy as well.
...
llvm-svn: 30973
2006-10-16 06:34:55 +00:00
b86375cfd0
Corrected load folding check. We need to start from the root of the sub-dag
...
being matched and ensure there isn't a non-direct path to the load (i.e. a
path that goes out of the sub-dag.)
llvm-svn: 30958
2006-10-14 08:33:25 +00:00
ab51cf2e78
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
...
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
a7956d2894
Doh. This wasn't causing problems by luck.
...
llvm-svn: 30914
2006-10-12 19:13:59 +00:00
40ec2bebf9
fix compilation failure of smg2000
...
llvm-svn: 30900
2006-10-12 03:55:48 +00:00
d5fcfaa6da
Fold "zero extending vector loads" now that evan added the chain manip stuff.
...
This compiles both tests in X86/vec_ss_load_fold.ll into:
_test1:
movss 4(%esp), %xmm0
subss LCPI1_0, %xmm0
mulss LCPI1_1, %xmm0
minss LCPI1_2, %xmm0
xorps %xmm1, %xmm1
maxss %xmm1, %xmm0
cvttss2si %xmm0, %eax
andl $65535, %eax
ret
instead of:
_test1:
movss LCPI1_0, %xmm0
movss 4(%esp), %xmm1
subss %xmm0, %xmm1
movss LCPI1_1, %xmm0
mulss %xmm0, %xmm1
movss LCPI1_2, %xmm0
minss %xmm0, %xmm1
xorps %xmm0, %xmm0
maxss %xmm0, %xmm1
cvttss2si %xmm1, %eax
andl $65535, %eax
ret
llvm-svn: 30894
2006-10-11 22:09:58 +00:00
4090dc4703
ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.
...
llvm-svn: 30892
2006-10-11 21:06:01 +00:00
61b8b43bbe
More isel time load folding checking for nodes that produce flag values.
...
See comment in CanBeFoldedBy() for detailed explanation.
llvm-svn: 30851
2006-10-10 01:46:56 +00:00
e71fe34d75
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
...
llvm-svn: 30844
2006-10-09 20:57:25 +00:00
398195ebbe
completely disable folding of loads into scalar sse instructions and provide
...
a framework for doing it right. This fixes
CodeGen/X86/2006-10-07-ScalarSSEMiscompile.ll.
Once X86DAGToDAGISel::SelectScalarSSELoad is implemented right, this task
will be done.
llvm-svn: 30817
2006-10-07 21:55:32 +00:00
1212b4d249
Not needed.
...
llvm-svn: 30674
2006-09-29 22:05:10 +00:00
6f7072c66a
Added some eye-candy for Subtarget type checking
...
Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
f8464da015
Remove a unnecessary check.
...
llvm-svn: 30382
2006-09-14 23:55:02 +00:00
706dd3e0d4
Fix a regression in the 32-bit port from the 64-bit port landing.
...
We now compile CodeGen/X86/lea-2.ll into:
_test:
movl 4(%esp), %eax
movl 8(%esp), %ecx
leal -5(%ecx,%eax,4), %eax
ret
instead of:
_test:
movl 4(%esp), %eax
leal (,%eax,4), %eax
addl 8(%esp), %eax
addl $4294967291, %eax
ret
llvm-svn: 30288
2006-09-13 04:45:25 +00:00
9a083a4121
Reflects MachineConstantPoolEntry changes.
...
llvm-svn: 30279
2006-09-12 21:04:05 +00:00
11b0a5dbd4
Committing X86-64 support.
...
llvm-svn: 30177
2006-09-08 06:48:29 +00:00
2c4e0f120f
Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen.
...
Suppose the TokenFactor can reach the Op:
[Load chain]
^
|
[Load]
^ ^
| |
/ \-
/ |
/ [Op]
/ ^ ^
| .. |
| / |
[TokenFactor] |
^ |
| |
\ /
\ /
[Store]
If we move the Load below the TokenFactor, we would have created a cycle in
the DAG.
llvm-svn: 30040
2006-09-01 22:52:28 +00:00
b28800f4d5
Remove dead code.
...
llvm-svn: 29962
2006-08-29 21:42:58 +00:00
dfb85155dc
Don't performance load/op/store transformation if op produces a floating point
...
or vector result. X86 does not have load/mod/store variants of those
instructions.
llvm-svn: 29957
2006-08-29 18:37:37 +00:00
358b9ed98a
- Enable x86 isel preprocessing by default unless -fast is specified.
...
- Also disable isel load folding if -fast.
llvm-svn: 29956
2006-08-29 18:28:33 +00:00
c07feb14b0
Avoid making unneeded load/mod/store transformation which can hurt performance.
...
llvm-svn: 29952
2006-08-29 06:44:17 +00:00
64a9e28846
Add an optional pass to preprocess the DAG before x86 isel to allow selecting more load/mod/store instructions.
...
llvm-svn: 29943
2006-08-28 20:10:17 +00:00
3d27be1333
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
...
llvm-svn: 29911
2006-08-27 12:54:02 +00:00
c3acfc0b10
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
...
SDOperand arguments. Use the variants which take an array and number instead.
llvm-svn: 29907
2006-08-27 08:14:06 +00:00
34b70eea5c
SelectNodeTo now returns a SDNode*.
...
llvm-svn: 29901
2006-08-26 08:00:10 +00:00
61413a3d72
Select() no longer require Result operand by reference.
...
llvm-svn: 29898
2006-08-26 05:34:46 +00:00
2d48722e92
Match tblgen changes; clean up.
...
llvm-svn: 29894
2006-08-26 01:05:16 +00:00
29ab7c42a8
Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tablegen.
...
llvm-svn: 29741
2006-08-16 23:59:00 +00:00
63d178f473
SelectNodeTo() may return a SDOperand that is different from the input.
...
llvm-svn: 29726
2006-08-16 07:30:09 +00:00
bd1c5a8fb8
Match tablegen changes.
...
llvm-svn: 29604
2006-08-11 09:08:15 +00:00
72bb66a4b8
Eliminate reachability matrix. It has to be calculated before any instruction
...
selection is done. That's rather expensive especially in situations where it
isn't really needed.
Move back to a searching the predecessors, but make use of topological order
to trim the search space.
llvm-svn: 29559
2006-08-08 00:31:00 +00:00
b9d34bd098
Match tablegen isel changes.
...
llvm-svn: 29549
2006-08-07 22:28:20 +00:00
8f585196e1
Reflect change to AssignTopologicalOrder().
...
llvm-svn: 29480
2006-08-02 22:01:32 +00:00
8101dd67d1
Use of vector<bool> causes some horrendous compile time regression (2x)!
...
Looks like libstdc++ implementation does not scale very well. Switch back
to using directly managed arrays.
llvm-svn: 29469
2006-08-02 09:18:33 +00:00
45af287957
Factor topological order code to SelectionDAG. Clean up.
...
llvm-svn: 29430
2006-08-01 08:17:22 +00:00
e8071ecc3b
Can't spell.
...
llvm-svn: 29383
2006-07-28 06:33:41 +00:00
2e94538b8e
Some clean up.
...
llvm-svn: 29382
2006-07-28 06:05:06 +00:00
e2a3f7014d
Rename IsFoldableBy to CanBeFoldedleBy
...
llvm-svn: 29376
2006-07-28 01:03:48 +00:00
11a4d8c2f4
Node selected into address mode cannot be folded.
...
llvm-svn: 29374
2006-07-28 00:49:31 +00:00
3b5e0cafd1
Another duh. Determine topological order before any target node is added.
...
llvm-svn: 29371
2006-07-28 00:10:59 +00:00
f38707b8d4
Brain cramp..
...
llvm-svn: 29370
2006-07-27 23:35:40 +00:00
390dd7eb7d
Allocating too large an array for ReachibilityMatrix.
...
llvm-svn: 29367
2006-07-27 22:35:40 +00:00
87585760ab
Calculate the portion of reachbility matrix on demand.
...
llvm-svn: 29366
2006-07-27 22:10:00 +00:00
d6c0c2dfd9
isNonImmUse is replaced by IsFoldableBy
...
llvm-svn: 29365
2006-07-27 21:19:10 +00:00
691a63d564
Use reachbility information to determine whether a node can be folded into another during isel.
...
llvm-svn: 29346
2006-07-27 16:44:36 +00:00
0cc5907728
Hide x86 symbols
...
llvm-svn: 28976
2006-06-28 23:27:49 +00:00
ba1ed585ee
Add support for "m" inline asm constraints.
...
llvm-svn: 28728
2006-06-08 18:03:49 +00:00
e8a42360c5
Cygwin support. Patch by Anton Korobeynikov!
...
llvm-svn: 28672
2006-06-02 22:38:37 +00:00
a2efb9f3ec
Use xor to clear a register.
...
llvm-svn: 28667
2006-06-02 21:20:34 +00:00
b33e54ead7
Remove bogus comment.
...
llvm-svn: 28564
2006-05-30 20:24:48 +00:00
734e1e241b
A addressing mode folding enhancement:
...
Fold c2 in (x << c1) | c2 where (c2 < c1)
e.g.
int test(int x) {
return (x << 3) + 7;
}
This can be codegen'd as:
leal 7(,%eax,8), %eax
llvm-svn: 28550
2006-05-30 06:59:36 +00:00
4af59dac0b
Assert if InflightSet is not cleared after instruction selecting a BB.
...
llvm-svn: 28459
2006-05-25 00:24:28 +00:00
1a8e74d113
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
...
non-deterministic behavior.
llvm-svn: 28454
2006-05-24 20:46:25 +00:00
aa2372562e
Patches to make the LLVM sources more -pedantic clean. Patch provided
...
by Anton Korobeynikov! This is a step towards closing PR786.
llvm-svn: 28447
2006-05-24 17:04:05 +00:00
85b6232b53
Back out indirect branch load folding hack. It broke some tests.
...
llvm-svn: 28425
2006-05-21 06:28:50 +00:00
401049ce33
- Use of load's chain result should be redirected to load's chain operand.
...
If it reads the chain result of the call, then the use, callseq_start,
and call would form a cycle!
- Don't forget handle node replacement!
- There could also be a TokenFactor between the load and the callseq_start.
llvm-svn: 28420
2006-05-20 09:21:39 +00:00
a26c451fa2
Missing break statements.
...
llvm-svn: 28418
2006-05-20 07:44:28 +00:00
b9ac06bb33
Remove unused patterns.
...
llvm-svn: 28417
2006-05-20 01:40:16 +00:00
f838cfcfbe
Handle indirect call which folds a load manually. This never matches by
...
the TableGen generated code since the load's chain result is read by
the callseq_start node.
llvm-svn: 28416
2006-05-20 01:36:52 +00:00
9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
...
llvm-svn: 28324
2006-05-16 07:21:53 +00:00
db30388d48
Remove dead code
...
llvm-svn: 28261
2006-05-12 19:03:56 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
...
movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
...
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
5d70a7c4a5
#include Intrinsics.h into all dag isels
...
llvm-svn: 27109
2006-03-25 06:47:10 +00:00
2dd2c652b2
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
...
llvm-svn: 26742
2006-03-13 23:20:37 +00:00
990c3602bd
Don't match x << 1 to LEAL. It's better to emit x + x.
...
llvm-svn: 26429
2006-02-28 21:13:57 +00:00
77d86ff8fc
* Cleaned up addressing mode matching code.
...
* Cleaned up and tweaked LEA cost analysis code. Removed some hacks.
* Handle ADD $X, c to MOV32ri $X+c. These patterns cannot be autogen'd and
they need to be matched before LEA.
llvm-svn: 26376
2006-02-25 10:09:08 +00:00
e0ed6ec13f
- Clean up the lowering and selection code of ConstantPool, GlobalAddress,
...
and ExternalSymbol.
- Use C++ code (rather than tblgen'd selection code) to match the above
mentioned leaf nodes. Do not mutate and nodes and do not record the
selection in CodeGenMap. These nodes should be safe to duplicate. This is
a performance win.
llvm-svn: 26335
2006-02-23 20:41:18 +00:00
1f342c2884
PIC related bug fixes.
...
1. Various asm printer bug.
2. Lowering bug. Now TargetGlobalAddress is wrapped in X86ISD::TGAWrapper.
llvm-svn: 26324
2006-02-23 02:43:52 +00:00
7eabbfd618
X86 codegen tweak to use lea in another case:
...
Suppose base == %eax and it has multiple uses, then instead of
movl %eax, %ecx
addl $8, %ecx
use
leal 8(%eax), %ecx.
llvm-svn: 26323
2006-02-23 00:13:58 +00:00
5588de9415
x86 / Darwin PIC support.
...
llvm-svn: 26273
2006-02-18 00:15:05 +00:00
a86ba85dc5
Prevent certain nodes that have already been selected from being folded into
...
X86 addressing mode. Currently we do not allow any node whose target node
produces a chain as well as any node that is at the root of the addressing
mode expression tree.
llvm-svn: 26117
2006-02-11 02:05:36 +00:00
2b6f78b664
Nicer code. :-)
...
llvm-svn: 26111
2006-02-10 22:46:26 +00:00
d49cc3634e
Added X86 isel debugging stuff.
...
llvm-svn: 26110
2006-02-10 22:24:32 +00:00
101e4b916a
Match tblgen change.
...
llvm-svn: 26096
2006-02-09 22:12:53 +00:00
d1b82d8db0
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
...
llvm-svn: 26085
2006-02-09 07:17:49 +00:00
6dc90ca172
Change Select() from
...
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
llvm-svn: 26067
2006-02-09 00:37:58 +00:00
d5f2ba0d6f
- Update load folding checks to match those auto-generated by tblgen.
...
- Manually select SDOperand's returned by TryFoldLoad which make up the
load address.
llvm-svn: 26012
2006-02-06 06:02:33 +00:00
54cb1833a4
Use SelectRoot() as entry of any tblgen based isel.
...
llvm-svn: 25997
2006-02-05 06:46:41 +00:00
d19d51f414
Re-commit the last bit of change that was backed out.
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llvm-svn: 25983
2006-02-05 05:25:07 +00:00
22b4edfb42
Temporarily revert this patch, which probably breaks with the
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tblgen patch reverted.
llvm-svn: 25971
2006-02-04 09:24:16 +00:00
ce87cac555
Complex pattern's custom matcher should not call Select() on any operands.
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Select them afterwards if it returns true.
llvm-svn: 25968
2006-02-04 08:50:49 +00:00
72d5c256c9
- Allow XMM load (for scalar use) to be folded into ANDP* and XORP*.
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- Use XORP* to implement fneg.
llvm-svn: 25857
2006-01-31 22:28:30 +00:00
cde9e30bc6
x86 CPU detection and proper subtarget support
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llvm-svn: 25679
2006-01-27 08:10:46 +00:00
de02d7727f
Add explicit #includes of <iostream>
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llvm-svn: 25515
2006-01-22 23:41:00 +00:00
6135a7a546
Didn't mean to check that in.
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llvm-svn: 25436
2006-01-19 01:52:56 +00:00
267ba5965e
A obvious typo
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llvm-svn: 25435
2006-01-19 01:46:14 +00:00
911c68d7a8
Fix FP_TO_INT**_IN_MEM lowering.
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llvm-svn: 25368
2006-01-16 21:21:29 +00:00
78c358d1ad
Use the default lowering of ISD::DYNAMIC_STACKALLOC, delete now dead code.
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llvm-svn: 25333
2006-01-15 09:00:21 +00:00
8869c6f782
silence a warning
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llvm-svn: 25322
2006-01-14 20:11:13 +00:00
2ae799aff0
Select DYNAMIC_STACKALLOC
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llvm-svn: 25225
2006-01-11 22:15:18 +00:00
bc7a0f44bd
* Add special entry code main() (to set x87 to 64-bit precision).
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* Allow a register node as SelectAddr() base.
* ExternalSymbol -> TargetExternalSymbol as direct function callee.
* Use X86::ESP register rather than CopyFromReg(X86::ESP) as stack ptr for
call parmater passing.
llvm-svn: 25207
2006-01-11 06:09:51 +00:00
7c551268d0
implement FP_REG_KILL insertion for the dag-dag instruction selector
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llvm-svn: 25192
2006-01-11 01:15:34 +00:00
29852a58b0
Fit into 80 cols
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llvm-svn: 25191
2006-01-11 00:46:55 +00:00
73a1ad975e
FP_TO_INT*_IN_MEM and x87 FP Select support.
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llvm-svn: 25188
2006-01-10 20:26:56 +00:00
7c4486215f
* Added undef patterns.
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* Some reorg.
llvm-svn: 25163
2006-01-09 23:10:28 +00:00
92e2797ce2
* Added integer div / rem.
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* Fixed a load folding bug.
llvm-svn: 25136
2006-01-06 23:19:29 +00:00
10d2790d50
ISEL code for MULHU, MULHS, and UNDEF.
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llvm-svn: 25132
2006-01-06 20:36:21 +00:00
b03f9b32d2
fold (shl x, 1) -> (add x, x)
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llvm-svn: 25120
2006-01-06 01:06:31 +00:00
a5ae6e8320
Added ConstantFP patterns.
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llvm-svn: 25108
2006-01-05 02:08:37 +00:00
45e19098a6
DAG based isel call support.
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llvm-svn: 25103
2006-01-05 00:27:02 +00:00
9cdc16c6d3
* Fix a GlobalAddress lowering bug.
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* Teach DAG combiner about X86ISD::SETCC by adding a TargetLowering hook.
llvm-svn: 24921
2005-12-21 23:05:39 +00:00
a2f308fc3e
Remove ISD::RET select code. Now tblgen'd.
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llvm-svn: 24889
2005-12-21 02:41:57 +00:00
a74ce62746
* Added lowering hook for external weak global address. It inserts a load
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for Darwin.
* Added lowering hook for ISD::RET. It inserts CopyToRegs for the return
value (or store / fld / copy to ST(0) for floating point value). This
eliminate the need to write C++ code to handle RET with variable number
of operands.
llvm-svn: 24888
2005-12-21 02:39:21 +00:00
1d9b671de0
It's essential we clear CodeGenMap after isel every basic block!
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llvm-svn: 24867
2005-12-19 22:36:02 +00:00
1d71248392
Darwin API issue: indirect load of external and weak symbols.
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llvm-svn: 24775
2005-12-17 09:13:43 +00:00
bc7708c0e8
Added truncate.
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llvm-svn: 24760
2005-12-17 02:02:50 +00:00
cb19390ead
Added support for cmp, test, and conditional move instructions.
...
llvm-svn: 24756
2005-12-17 01:24:02 +00:00
74151ba279
* Promote all 1 bit entities to 8 bit.
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* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.
llvm-svn: 24726
2005-12-15 19:49:23 +00:00
00fcb0017e
Handling zero extension of 1 bit value.
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llvm-svn: 24722
2005-12-15 01:02:48 +00:00
67ed58e22b
When SelectLEAAddr() fails, it shouldn't cause the side effect of having the
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base or index operands being selected.
llvm-svn: 24674
2005-12-12 21:49:40 +00:00
bfd259a2b7
For ISD::RET, if # of operands >= 2, try selection the real data dep. operand
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first before the chain.
e.g.
int X;
int foo(int x)
{
x += X + 37;
return x;
}
If chain operand is selected first, we would generate:
movl X, %eax
movl 4(%esp), %ecx
leal 37(%ecx,%eax), %eax
rather than
movl $37, %eax
addl 4(%esp), %eax
addl X, %eax
which does not require %ecx. (Due to ADD32rm not matching.)
llvm-svn: 24673
2005-12-12 20:32:18 +00:00
0d6cfee704
* Added X86 store patterns.
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* Added X86 dec patterns.
llvm-svn: 24654
2005-12-10 00:48:20 +00:00
c9fab31098
* Added intelligence to X86 LEA addressing mode matching routine so it returns
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false if the match is not profitable. e.g. leal 1(%eax), %eax.
* Added patterns for X86 integer loads and LEA32.
llvm-svn: 24635
2005-12-08 02:01:35 +00:00
4b02426130
Proper support for shifts with register shift value.
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llvm-svn: 24559
2005-12-01 00:43:55 +00:00
af2e0373dd
SelectNodeTo now returns its result, we must pay attention to it.
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llvm-svn: 24550
2005-11-30 22:59:19 +00:00
4eb7af9bc9
Added support to STORE and shifts to DAG to DAG isel.
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llvm-svn: 24525
2005-11-30 02:51:20 +00:00
3f0f71b92b
Add load and other support to the dag-dag isel. Patch contributed by Evan
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Cheng!
llvm-svn: 24419
2005-11-19 02:11:08 +00:00
5930d3df3d
Add patterns for several simple instructions that take i32 immediates.
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Patch contributed by Evan Cheng!
llvm-svn: 24382
2005-11-16 22:59:19 +00:00
655e7dfd0d
initial step at adding a dag-to-dag isel for X86 backend. Patch contributed
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by Evan Cheng!
llvm-svn: 24371
2005-11-16 01:54:32 +00:00
Dale Johannesen