Commit Graph

128417 Commits

Author SHA1 Message Date
Sanjay Patel f831fdb56a fix variable name; NFC
llvm-svn: 262953
2016-03-08 19:07:42 +00:00
Sanjay Patel 5c96723622 use range-based loop; NFCI
llvm-svn: 262952
2016-03-08 19:06:12 +00:00
Hans Wennborg af845d79ad Add self to CODE_OWNERS
Apparently this makes my email address easier to find.

llvm-svn: 262951
2016-03-08 19:01:15 +00:00
Saleem Abdulrasool 2d5e95c00d cmake: include what you use
Add a missing include.  This is important in the case HandleLLVMOptions is
included prior to the missing CheckCXXSourceCompiles or CheckCXXCompilerFlag
which includes CheckCXXSourceCompiles.

llvm-svn: 262949
2016-03-08 18:56:00 +00:00
Chris Bieneman 74c98f0e8d [CMake] Refactor add_llvm_implicit_projects to be reusable
This adds llvm_add_implicit_projects which takes a project name and is wrapped by add_llvm_implicit_projects.

llvm-svn: 262948
2016-03-08 18:43:28 +00:00
Chad Rosier 2a70624403 [AArch64] Disable the MI scheduler to turn bots green after r262942.
llvm-svn: 262944
2016-03-08 17:33:34 +00:00
Quentin Colombet 4340b55593 Revert r262759 and r262760.
The fix consisting in using the library call for atomic compare and swap when
the instruction is not safe to use may be incorrect. Indeed the library call may
not exist on all platform. In other words, we need a better fix! 

llvm-svn: 262943
2016-03-08 17:29:11 +00:00
Chad Rosier e40b9513a9 [AArch64] Add MMOs to unscaled pairs.
Test to be committed in follow up commit, per discussion in D17097.
http://reviews.llvm.org/D17097

llvm-svn: 262942
2016-03-08 17:16:38 +00:00
Sanjay Patel eaf06851d0 rangify, fix function names; NFCI
llvm-svn: 262940
2016-03-08 17:12:32 +00:00
Krzysztof Parzyszek cd99e364e3 Invoke DAG postprocessing in the post-RA scheduler
This was inadvertently omitted from r262774, which added the mutation
interface.

llvm-svn: 262939
2016-03-08 16:54:20 +00:00
Sanjay Patel 5b8d741632 don't repeat function names in documentation comments; NFC
llvm-svn: 262937
2016-03-08 16:26:39 +00:00
Artyom Skrobov 5ddea6a8e9 [ARM] Simplify ARMInstr*.td by getting rid of identity PatFrags (NFC)
Reviewers: t.p.northover, grosbach, resistor

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D17636

llvm-svn: 262936
2016-03-08 16:23:54 +00:00
Hans Wennborg e00b6e7249 Revert r262599 "[X86][SSE] Improve vector ZERO_EXTEND by combining to ZERO_EXTEND_VECTOR_INREG"
This caused PR26870.

llvm-svn: 262935
2016-03-08 16:21:41 +00:00
Manuel Klimek 43a43079a6 Fix problem with uninitilialized bool found by asan.
llvm-svn: 262934
2016-03-08 16:17:48 +00:00
Krzysztof Parzyszek 1a1d78b86f Add DAG mutation interface to the DFA packetizer
llvm-svn: 262930
2016-03-08 15:33:51 +00:00
Igor Breger 999ac754f2 AVX512: Add extract_subvector patterns v8i1->v4i1 , v4i1->v2i1.
Differential Revision: http://reviews.llvm.org/D17953

llvm-svn: 262929
2016-03-08 15:21:25 +00:00
Benjamin Kramer 39988a03a5 [gold] Avoid assertion failures when taking a pointer to an empty vector.
llvm-svn: 262926
2016-03-08 14:02:46 +00:00
Filipe Cabecinhas a7e63b1e67 [llvm-config] Get rid of code related to the Makefile builds
Summary: I left --build-system for backwards compat, in case there are scripts using it. Feel free to ask for its removal too.

Reviewers: chapuni, tstellarAMD

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17886

llvm-svn: 262924
2016-03-08 11:49:24 +00:00
Simon Pilgrim d8ac7c9f2d [X86] Regenerated vector float extension tests
llvm-svn: 262919
2016-03-08 09:17:12 +00:00
Junmo Park 3452d33ae2 Remove pr25342 test-case.
This commit removes pr25342 for reverting r262670 clearly.

llvm-svn: 262918
2016-03-08 07:42:12 +00:00
Junmo Park 974eb0a96d Revert "[InstCombine] Combine A->B->A BitCast"
This reverts commit r262670 due to compile failure.

llvm-svn: 262916
2016-03-08 07:09:46 +00:00
Justin Bogner 6e2b99516a SelectionDAG: Appease the bots that don't like my union
Should fix the breakage in r262902.

llvm-svn: 262908
2016-03-08 03:51:58 +00:00
Peter Collingbourne 3866cc5f69 Fix evaluation order. Spotted by Alexander Riccio!
llvm-svn: 262907
2016-03-08 03:50:36 +00:00
Kit Barton ba532dc816 [Power9] Implement new vsx instructions: load, store instructions for vector and scalar
We follow the comments mentioned in http://reviews.llvm.org/D16842#344378 to
implement this new patch.

This patch implements the following vsx instructions:

Vector load/store:
lxv lxvx lxvb16x lxvl lxvll lxvh8x lxvwsx
stxv stxvb16x stxvh8x stxvl stxvll stxvx
Scalar load/store:
lxsd lxssp lxsibzx lxsihzx
stxsd stxssp stxsibx stxsihx
21 instructions

Phabricator: http://reviews.llvm.org/D16919
llvm-svn: 262906
2016-03-08 03:49:13 +00:00
Dan Gohman 1402606477 [WebAssembly] Update for spec change from tableswitch to br_table.
Also note that the operand order changed; the default label is now listed
after the regular labels.

llvm-svn: 262903
2016-03-08 03:18:12 +00:00
Justin Bogner 671febc0f7 Re-apply "SelectionDAG: Store SDNode operands in an ArrayRecycler"
This re-applies r262886 with a fix for 32 bit platforms that have 8 byte
pointer alignment, effectively reverting r262892.

Original Message:

  Currently some SDNode operands are malloc'd, some are stored inline in
  subclasses of SDNode, and some are thrown into a BumpPtrAllocator.
  This scheme is complex, inconsistent, and makes refactoring SDNodes
  fairly difficult.

  Instead, we can allocate all of the operands using an ArrayRecycler
  that wraps a BumpPtrAllocator. This keeps the cache locality when
  iterating operands, improves locality when iterating SDNodes without
  looking at operands, and vastly simplifies the ownership semantics.

  It also means we stop overallocating SDNodes by 2-3x and will make it
  simpler to fix the rampant undefined behaviour we have in how we
  mutate SDNodes from one kind to another (See llvm.org/pr26808).

  This is NFC other than the changes in memory behaviour, and I ran some
  LNT tests to make sure this didn't hurt compile time. Not many tests
  changed: there were a couple of 1-2% regressions reported, but there
  were more improvements (of up to 4%) than regressions.

llvm-svn: 262902
2016-03-08 03:14:29 +00:00
Quentin Colombet 5e63e78ca9 [MIR] Change the token name for '<' and '>' to be consitent with the LLVM IR parser.
Thanks to Ahmed Bougacha for noticing!

llvm-svn: 262899
2016-03-08 02:00:43 +00:00
Quentin Colombet dca821683c [AArch64][GlobalISel] Add a test case for the IRTranslator.
llvm-svn: 262898
2016-03-08 01:48:08 +00:00
Quentin Colombet f574ab292b [AArch64] Initialize GlobalISel as part of the target initialization.
llvm-svn: 262897
2016-03-08 01:45:36 +00:00
Quentin Colombet 39293d3aaa [GlobalISel] Introduce initializer method to support start/stop-after features.
llvm-svn: 262896
2016-03-08 01:38:55 +00:00
Quentin Colombet 050b211820 [MIR] Teach the parser/printer that generic virtual registers do not need a register class.
llvm-svn: 262893
2016-03-08 01:17:03 +00:00
Justin Bogner 7e6f09c28f Revert "SelectionDAG: Store SDNode operands in an ArrayRecycler"
Looks like the largest SDNode is different between 32 and 64 bit now,
so this is breaking 32 bit bots. Reverting while I figure out a fix.

This reverts r262886.

llvm-svn: 262892
2016-03-08 01:07:03 +00:00
Richard Smith c2a2830e94 A couple more UB fixes for C++14 sized deallocation.
llvm-svn: 262891
2016-03-08 00:59:44 +00:00
Quentin Colombet 287c6bb571 [MIR] Teach the parser how to parse complex types of generic machine instructions.
By complex types, I mean aggregate or vector types.

llvm-svn: 262890
2016-03-08 00:57:31 +00:00
Justin Bogner 6543a9385f SelectionDAG: Store SDNode operands in an ArrayRecycler
Currently some SDNode operands are malloc'd, some are stored inline in
subclasses of SDNode, and some are thrown into a BumpPtrAllocator.
This scheme is complex, inconsistent, and makes refactoring SDNodes
fairly difficult.

Instead, we can allocate all of the operands using an ArrayRecycler
that wraps a BumpPtrAllocator. This keeps the cache locality when
iterating operands, improves locality when iterating SDNodes without
looking at operands, and vastly simplifies the ownership semantics.

It also means we stop overallocating SDNodes by 2-3x and will make it
simpler to fix the rampant undefined behaviour we have in how we
mutate SDNodes from one kind to another (See llvm.org/pr26808).

This is NFC other than the changes in memory behaviour, and I ran some
LNT tests to make sure this didn't hurt compile time. Not many tests
changed: there were a couple of 1-2% regressions reported, but there
were more improvements (of up to 4%) than regressions.

llvm-svn: 262886
2016-03-08 00:39:51 +00:00
Quentin Colombet d655483944 [MIR] Teach the printer how to print complex types for generic machine instructions.
Before this change, we would get the type definition in the middle
of the instruction.
E.g., %0(48) = G_ADD %struct_alias = type { i32, i16 } %edi, %edi

Now, we have just the expected type name:
%0(48) = G_ADD %struct_alias %edi, %edi

llvm-svn: 262885
2016-03-08 00:38:01 +00:00
Quentin Colombet dafed5d7d8 [AsmParser] Expose an API to parse a string starting with a type.
Without actually parsing a type it is difficult to perdict where
the type definition ends. In other words, instead of expecting
the user of the parser API to hand over only the relevant bits
of the string being parsed, take the whole string, parse the type,
and get back the number of characters that have been read.

This will be used by the MIR testing infrastructure.

llvm-svn: 262884
2016-03-08 00:37:07 +00:00
Easwaran Raman b1bd398ceb Revert revisions 262636, 262643, 262679, and 262682.
llvm-svn: 262883
2016-03-08 00:36:35 +00:00
Quentin Colombet 12350a8e13 [MIR] Print the type of generic machine instructions.
llvm-svn: 262880
2016-03-08 00:29:15 +00:00
Quentin Colombet 851996778f [MIR] Teach the mir parser about types on generic machine instructions.
llvm-svn: 262879
2016-03-08 00:20:48 +00:00
Quentin Colombet 9d1bc8bd16 [lit] Teach lit about global-isel requirement.
llvm-svn: 262878
2016-03-08 00:03:40 +00:00
Quentin Colombet 447f852aa9 [llvm-config] Teach llvm-config about global-isel.
llvm-config can know tell whether or not a build has been configured to support
global-isel.
Use '--has-global-isel' for that.

llvm-svn: 262877
2016-03-08 00:02:50 +00:00
Anna Zaks c1efa64c63 [tsan] Add support for pointer typed atomic stores, loads, and cmpxchg
TSan instrumentation functions for atomic stores, loads, and cmpxchg work on
integer value types. This patch adds casts before calling TSan instrumentation
functions in cases where the value is a pointer.

Differential Revision: http://reviews.llvm.org/D17833

llvm-svn: 262876
2016-03-07 23:16:23 +00:00
Sanjay Patel 8c84f74f3a [x86] add test to show missing optimization
This should make it clearer how this proposed patch:
http://reviews.llvm.org/D11393
...will change codegen.

llvm-svn: 262875
2016-03-07 23:13:06 +00:00
Sanjay Patel 55c0dd4b26 [x86] simplify test and tighten checks
I noticed this test as part of:
http://reviews.llvm.org/D11393
...which is confusing enough as-is. 
Let's show the exact codegen, so the changes will be more obvious.

llvm-svn: 262874
2016-03-07 22:53:23 +00:00
Quentin Colombet 41bea872dd [MachineInstr] Get rid of some GlobalISel ifdefs.
Now the type API is always available, but when global-isel is not
built the implementation does nothing.

Note: The implementation free of ifdefs is WIP and tracked here in PR26576.
llvm-svn: 262873
2016-03-07 22:47:23 +00:00
Amaury Sechet b813e4d4ae Remove unused import in Orc C API
Summary: It is not used.

Reviewers: lhames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D17251

llvm-svn: 262870
2016-03-07 22:40:07 +00:00
Quentin Colombet 774b1efa62 [IR] Provide an API to skip the details of a structured type when printed.
The mir infrastructure will need this for generic instructions and currently
this feature was only available through the anonymous TypePrinter class.

llvm-svn: 262869
2016-03-07 22:32:42 +00:00
Quentin Colombet 81e72b4d4e [AsmParser] Add a function to parse a standalone type.
This is useful for MIR serialization. Indeed generic machine instructions
must have a type and we don't want to duplicate the logic in the MIParser.

llvm-svn: 262868
2016-03-07 22:09:05 +00:00
Quentin Colombet 4e14a497a3 [MIR] Teach the MIPrinter about size for generic virtual registers.
llvm-svn: 262867
2016-03-07 21:57:52 +00:00