Commit Graph

184 Commits

Author SHA1 Message Date
Tom Stellard aec94b3bf3 R600/SI: Add missing mubuf instructions
llvm-svn: 230759
2015-02-27 14:59:46 +00:00
Tom Stellard 49282c92c5 R600/SI: Consistently put soffset before the offset operand for mubuf instructions
This matches the assembly syntax.

llvm-svn: 230758
2015-02-27 14:59:44 +00:00
Tom Stellard 1f9939fba6 R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructions
llvm-svn: 230757
2015-02-27 14:59:41 +00:00
Tom Stellard eb05c610b4 R600/SI: Remove M0 from DS assembly strings
This matches the assembly syntax for the proprietary compiler.

llvm-svn: 230645
2015-02-26 17:08:43 +00:00
Matt Arsenault 70120fa813 R600/SI: Fix mad*k definitions
llvm-svn: 230146
2015-02-21 21:29:00 +00:00
Tom Stellard 1ca873bbc5 R600/SI: Don't set isCodeGenOnly = 1 on all instructions
We only need to set this on pseudo instructions which won't
be used by the assembler.

llvm-svn: 229689
2015-02-18 16:08:17 +00:00
Tom Stellard c34c37ae66 R600/SI: Add missing VOP1 instructions
llvm-svn: 229688
2015-02-18 16:08:15 +00:00
Tom Stellard 0c0008cb6e R600/SI: Add definition for S_CBRANCH_G_FORK
llvm-svn: 229686
2015-02-18 16:08:13 +00:00
Tom Stellard ce449ade7e R600/SI: Add missing SOP1 instructions
llvm-svn: 229685
2015-02-18 16:08:11 +00:00
Tom Stellard ee21faa029 R600/SI: Refactor SOP2 definitions
llvm-svn: 229684
2015-02-18 16:08:09 +00:00
Matt Arsenault e3dbcf6656 R600/SI: Consistently capitalize encoding field names
Some formats capitalized these, but most didn't. Change
them all to be consistently lowercase.

Now, non-encoding fields and convenience bits are capitalized.
Also remove weird looking empty line in some of the formats.

llvm-svn: 229613
2015-02-18 02:15:35 +00:00
Matt Arsenault 096ec1e10c R600/SI: Fix src1_modifiers for class instructions
src1 doesn't have modifiers, but the operand was missing
resulting in an encoding build error when all fields
are required.'

llvm-svn: 229611
2015-02-18 02:15:30 +00:00
Matt Arsenault 65fa1c425d R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64
Rename the multiclass since it now applies to the output
modifiers as well.

llvm-svn: 229610
2015-02-18 02:15:27 +00:00
Matt Arsenault 1991f5e40b R600/SI: Fix encoding error from glc bit on VI SMRD instructions
llvm-svn: 229608
2015-02-18 02:10:40 +00:00
Matt Arsenault e6c5241814 R600/SI: Fix operand encoding for flat instructions
llvm-svn: 229607
2015-02-18 02:10:37 +00:00
Matt Arsenault 07e3bb153f R600/SI: Fix error from vdst on no return atomics
Set the ignored field to 0 so we can enable
noNamedPositionallyEncodedOperands.

llvm-svn: 229606
2015-02-18 02:10:35 +00:00
Matt Arsenault caa1288fff R600/SI: Add missing offset operand to buffer bothen
llvm-svn: 229605
2015-02-18 02:04:38 +00:00
Matt Arsenault 2ad8bab7ee R600/SI: Add missing soffset operand to global atomics
llvm-svn: 229604
2015-02-18 02:04:35 +00:00
Matt Arsenault 1bc9d95047 R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation.

Test is disabled for VI since there seems to be a problem with one
of the buffer load instructions on it.

llvm-svn: 229236
2015-02-14 04:22:00 +00:00
Matt Arsenault 31ec598a2a R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}
This apparently got lost in the VI changes.

llvm-svn: 229230
2015-02-14 03:40:35 +00:00
Matt Arsenault 692acf1438 R600/SI: Fix VOP3b encoding on VI
llvm-svn: 229228
2015-02-14 03:02:23 +00:00
Tom Stellard e1e4a2d310 R600/SI: Refactor SOP1 classes
llvm-svn: 229152
2015-02-13 21:02:37 +00:00
Tom Stellard d09fa9cec8 R600/SI: Remove some unused TableGen classes
llvm-svn: 229150
2015-02-13 21:02:33 +00:00
Tom Stellard c53861ab84 R600/SI: Add soffset operand to mubuf addr64 instruction
We were previously hard-coding soffset to 0.

llvm-svn: 228775
2015-02-11 00:34:32 +00:00
Michel Danzer 494391ba47 R600/SI: Also enable WQM for image opcodes which calculate LOD v3
If whole quad mode isn't enabled for these, the level of detail is
calculated incorrectly for pixels along diagonal triangle edges, causing
artifacts.

v2: Use a TSFlag instead of lots of switch cases
v3: Add test coverage

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642
Reviewed-by: Tom Stellard <tom@stellard.net>
llvm-svn: 228372
2015-02-06 02:51:20 +00:00
Marek Olsak 3ecf508734 R600/SI: Rewrite VOP1InstSI to contain a pseudo and _si opcode
What this does is that if you accidentally select these instructions on VI,
the code generation will fail, because the pseudo -> _vi mapping will be
undefined.

The idea is to be able to catch possible future bugs easily.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 228038
2015-02-03 21:53:05 +00:00
Marek Olsak 707a6d0c20 R600/SI: Fix B64 VALU shifts on VI
SI only has standard versions. VI only has REV versions.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 228037
2015-02-03 21:53:01 +00:00
Marek Olsak 191507e0b7 R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI
This can happen when a REV instruction is commuted.

The trick is not to define the _vi versions of instructions, which has these
consequences:
- code generation will always fail if a pseudo cannot be lowered
  (very useful to catch bugs where an unsupported instruction somehow makes
   it to the printer)
- ability to query if a pseudo can be lowered, which is done in commuteOpcode
  to prevent REV from commuting to non-REV on VI

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 227990
2015-02-03 17:38:12 +00:00
Marek Olsak 7585a29bd4 R600/SI: Remove VOP2_REV definitions from target-specific instructions
The getCommute* functions are only used with pseudos, so this commit doesn't
change anything.

The issue with missing non-rev versions of shift instructions on VI will fixed
separately.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 227989
2015-02-03 17:38:05 +00:00
Marek Olsak 11057ee022 R600/SI: Trivial instruction definition corrections for VI (v2)
- V_MAC_LEGACY_F32 exists on VI, but it's VOP3-only.

- Define CVT_PK opcodes which are different between SI and VI. These are
  unused. The idea is to define all chip differences.

v2: keep V_MUL_LO_U32

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 227988
2015-02-03 17:38:01 +00:00
Eric Christopher 7792e32b64 Reuse a bunch of cached subtargets and remove getSubtarget calls
without a Function argument.

llvm-svn: 227638
2015-01-30 23:24:40 +00:00
Marek Olsak 367447c255 R600/SI: Don't set patterns for chip-specific instructions while having pseudos
Only pseudos have patterns on them.

Also don't set the asm string for VINTRP_Pseudo. All pseudos should have empty
asm.

This matches what all other multiclasses do.

llvm-svn: 227212
2015-01-27 17:25:11 +00:00
Marek Olsak 0c1f8812f5 R600/SI: Add VI versions of LDS atomics
Each class is split into two: one adds let statements around non-pseudos,
and the other one specifies the parameters.

llvm-svn: 227211
2015-01-27 17:25:07 +00:00
Marek Olsak 19d9e1f459 R600/SI: Add VI versions of MUBUF atomics
llvm-svn: 227210
2015-01-27 17:25:02 +00:00
Marek Olsak ee98b1177c R600/SI: Add VI versions of MUBUF loads and stores
This enables a lot of existing patterns for VI.

llvm-svn: 227209
2015-01-27 17:24:58 +00:00
Marek Olsak 7ef6db49ac R600/SI: Add pseudos for MUBUF loads and stores
This defines the SI versions only, so it shouldn't change anything.

There are no changes other than using the new multiclasses, adding missing
mayLoad/mayStore, and formatting fixes.

llvm-svn: 227208
2015-01-27 17:24:54 +00:00
Matt Arsenault 268757ba60 R600/SI: Fix trailing comma with modifiers
Instructions with 1 operand can still use source modifiers,
so make sure we don't print an extra comma afterwards.

llvm-svn: 226226
2015-01-15 23:17:03 +00:00
Marek Olsak f0b130ace0 R600/SI: Unify VOP2 instructions which are VOP3-only on VI
This removes some duplicated classes and definitions.

These instructions are defined:
  _e32 // pseudo
  _e32_si
  _e64 // pseudo
  _e64_si
  _e64_vi

llvm-svn: 226191
2015-01-15 18:43:06 +00:00
Marek Olsak 15e4a59899 R600/SI: Add V_READLANE_B32 and V_WRITELANE_B32 for VI
These are VOP3-only on VI.

The new multiclass doesn't define VOP3 versions of VOP2 instructions.

llvm-svn: 226189
2015-01-15 18:42:55 +00:00
Marek Olsak a93603d508 R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
v2: modify hasVALU32BitEncoding instead
v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both
      hasVALU32BitEncoding and AMDGPUMCInstLower::lower
    - report an error if a pseudo can't be lowered
llvm-svn: 226188
2015-01-15 18:42:51 +00:00
Tom Stellard 42fb60e1a7 R600/SI: Spill VGPRs to scratch space for compute shaders
llvm-svn: 225988
2015-01-14 15:42:31 +00:00
Tom Stellard fb77f00be8 R600/SI: Add pattern for bitcasting fp immediates to integers
The backend now assumes that all immediates are integers.  This allows
us to simplify immediate handling code, becasue we no longer need to
handle fp and integer immediates differently.

llvm-svn: 225844
2015-01-13 22:59:41 +00:00
Tom Stellard b6550529a6 R600/SI: Use RegisterOperands to specify which operands can accept immediates
There are some operands which can take either immediates or registers
and we were previously using different register class to distinguish
between operands that could take immediates and those that could not.

This patch switches to using RegisterOperands which should simplify the
backend by reducing the number of register classes and also make it
easier to implement the assembler.

llvm-svn: 225662
2015-01-12 19:33:18 +00:00
Tom Stellard 45c0b3a882 R600/SI: Remove VReg_32 register class
Use VGPR_32 register class instead.  These two register classes were
identical and having separate classes was causing
SIInstrInfo::isLegalOperands() to be overly conservative in some cases.

This change is necessary to prevent future paches from missing a folding
opportunity in fneg-fabs.ll.

llvm-svn: 225382
2015-01-07 20:59:25 +00:00
Matt Arsenault 4831ce5491 R600/SI: Add class intrinsic
llvm-svn: 225305
2015-01-06 23:00:37 +00:00
Tom Stellard c3d7eeb6e5 R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand
mubuf instructions now define the soffset field using the SCSrc_32
register class which indicates that only SGPRs and inline constants
are allowed.

llvm-svn: 224622
2014-12-19 22:15:30 +00:00
Matt Arsenault 303011a005 R600/SI: Fix f64 inline immediates
llvm-svn: 224458
2014-12-17 21:04:08 +00:00
Tom Stellard 3e41dc419c R600/SI: Set MayStore = 0 on MUBUF loads
llvm-svn: 223722
2014-12-09 00:03:54 +00:00
Tom Stellard 3260ec41cf R600/SI: Move setting of the lds bit to the base MUBUF class
llvm-svn: 223721
2014-12-09 00:03:51 +00:00
Marek Olsak 58f61a84e7 R600/SI: Set 20-bit immediate byte offset for SMRD on VI
llvm-svn: 223614
2014-12-07 17:17:38 +00:00