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8 Commits

Author SHA1 Message Date
Matt Arsenault 0bbcd8ba2f R600/SI: Implement correct f64 fdiv 
This version passes the OpenCL conformance test.

llvm-svn: 229239
 2015-02-14 04:30:08 +00:00
Eric Christopher 7792e32b64 Reuse a bunch of cached subtargets and remove getSubtarget calls 
without a Function argument.

llvm-svn: 227638
 2015-01-30 23:24:40 +00:00
Matt Arsenault 9acb978105 R600: Match rcp node on pre-SI 
llvm-svn: 213844
 2014-07-24 06:59:24 +00:00
Matt Arsenault 493c5f1bc4 R600: Expand mul24 for GPUs without it 
llvm-svn: 209458
 2014-05-22 18:00:24 +00:00
Matt Arsenault f15a05623e R600: Expand mad24 for GPUs without it 
llvm-svn: 209457
 2014-05-22 18:00:20 +00:00
Matt Arsenault eb260206c3 R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Tom Stellard 50122a5890 R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731
 2014-04-07 19:45:41 +00:00
Tom Stellard 2c1c9de151 R600: Reorganize tablegen instruction definitions 
Each GPU family now has its own file.

llvm-svn: 204615
 2014-03-24 16:07:25 +00:00