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224 Commits

Author SHA1 Message Date
Vincent Lejeune 3a8d78a2c3 R600: Always use texture cache for compute shaders 
This will improve the performance of memory reads.

llvm-svn: 180762
 2013-04-30 00:14:44 +00:00
Vincent Lejeune 3abdbf1cad R600: use native for alu 
llvm-svn: 180761
 2013-04-30 00:14:38 +00:00
Vincent Lejeune 147700b8b4 R600: Packetize instructions 
llvm-svn: 180760
 2013-04-30 00:14:27 +00:00
Vincent Lejeune 076c0b28e3 R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips 
llvm-svn: 180759
 2013-04-30 00:14:17 +00:00
Vincent Lejeune 22c4248213 R600: Add a Bank Swizzle operand 
llvm-svn: 180758
 2013-04-30 00:14:08 +00:00
Vincent Lejeune 7c395f77de R600: Take inner dependency into tex/vtx clauses 
llvm-svn: 180757
 2013-04-30 00:14:00 +00:00
Vincent Lejeune 3f1d136b02 R600: Turn TEX/VTX into native instructions 
llvm-svn: 180756
 2013-04-30 00:13:53 +00:00
Vincent Lejeune c299164284 R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions 
v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache

llvm-svn: 180755
 2013-04-30 00:13:39 +00:00
Vincent Lejeune 7d820c0bef R600: Add some new processor variants 
llvm-svn: 180753
 2013-04-30 00:13:27 +00:00
Vincent Lejeune f501ea298b R600: Clean up instruction class definitions 
llvm-svn: 180752
 2013-04-30 00:13:20 +00:00
Vincent Lejeune 4a0beb5207 R600: config section now reports use of killgt 
llvm-svn: 180751
 2013-04-30 00:13:13 +00:00
Tom Stellard 119ad03c67 R600: Use correct CF_END instruction on Northern Island GPUs 
llvm-svn: 180735
 2013-04-29 22:23:58 +00:00
Tom Stellard 8367067e02 R600: Fix encoding of CF_END_{EG, R600} instructions 
The EOP bit was not being encoded.

llvm-svn: 180734
 2013-04-29 22:23:54 +00:00
Tom Stellard 456adc6c4e R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTE 
We need to intialize this to something and since clang does not set
the shader type attribute and clang is used only for compute shaders,
initializing it to COMPUTE seems like the best choice.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 180620
 2013-04-26 18:32:24 +00:00
Tom Stellard 87047f69ad R600: Initialize BooleanVectorContents 
Fixes test/CodeGen/R600/setcc.ll

llvm-svn: 180231
 2013-04-24 23:56:18 +00:00
Tom Stellard 34e4068d05 R600: Use SHT_PROGBITS for the .AMDGPU.config section 
The libelf implementation that is distributed here:
http://www.mr511.de/software/english.html
will not parse sections that are marked SHT_NULL.

llvm-svn: 180230
 2013-04-24 23:56:14 +00:00
Vincent Lejeune 117f075f6e R600: Use .AMDGPU.config section to emit stacksize 
llvm-svn: 180124
 2013-04-23 17:34:12 +00:00
Vincent Lejeune b6bfe85a07 R600: Add CF_END 
llvm-svn: 180123
 2013-04-23 17:34:00 +00:00
Matt Arsenault 034ca0fe41 Remove unused DwarfSectionOffsetDirective string 
The value isn't actually used, and setting it emits a COFF specific
directive.

llvm-svn: 180064
 2013-04-22 22:49:11 +00:00
Michael Liao b53d8963ce ArrayRefize getMachineNode(). No functionality change. 
llvm-svn: 179901
 2013-04-19 22:22:57 +00:00
Tom Stellard 9d10c4ce86 R600: Add pattern for the BFI_INT instruction 
llvm-svn: 179830
 2013-04-19 02:11:06 +00:00
Tom Stellard ea977bc0e3 R600/SI: Use InstFlag for VOP3 modifier operands 
InstFlag has a default value of 0 and will simplify the VOP3 patterns.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179829
 2013-04-19 02:11:00 +00:00
Vincent Lejeune 2d5c341cee R600: Make Export Instruction not duplicable 
llvm-svn: 179686
 2013-04-17 15:17:39 +00:00
Vincent Lejeune 218093e834 R600: Export is emitted as a CF_NATIVE inst 
llvm-svn: 179685
 2013-04-17 15:17:32 +00:00
Vincent Lejeune 98a7380859 R600: Emit used GPRs count 
llvm-svn: 179684
 2013-04-17 15:17:25 +00:00
Tom Stellard cb97e3acfa R600/SI: Emit config values in register value pairs. 
Instead of emitting config values in a predefined order, the code
emitter will now emit a 32-bit register index followed by the 32-bit
config value.

llvm-svn: 179546
 2013-04-15 17:51:35 +00:00
Tom Stellard 3a7beafb32 R600/SI: Emit configuration value in the .AMDGPU.config ELF section 
llvm-svn: 179545
 2013-04-15 17:51:30 +00:00
Tom Stellard 9991659fab R600: Emit ELF formatted code rather than raw ISA. 
llvm-svn: 179544
 2013-04-15 17:51:21 +00:00
NAKAMURA Takumi 3ee2b1e26f R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable] 
llvm-svn: 179263
 2013-04-11 04:16:27 +00:00
NAKAMURA Takumi 3b0853be56 Whitespace. 
llvm-svn: 179262
 2013-04-11 04:16:22 +00:00
Michel Danzer 8caa904bde R600/SI: Add pattern for AMDGPUurecip 
21 more little piglits with radeonsi.

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 179186
 2013-04-10 17:17:56 +00:00
Vincent Lejeune 04d9aa4822 R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addr 
llvm-svn: 179174
 2013-04-10 13:29:20 +00:00
Christian Konig 8b1ed28ef1 R600/SI: dynamical figure out the reg class of MIMG 
Depending on the number of bits set in the writemask.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179166
 2013-04-10 08:39:16 +00:00
Christian Konig 8e06e2a8c4 R600/SI: adjust writemask to only the used components 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179165
 2013-04-10 08:39:08 +00:00
Christian Konig 4ace663255 R600/SI: remove image sample writemask 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
llvm-svn: 179164
 2013-04-10 08:39:01 +00:00
Vincent Lejeune 5f11dd390a R600: Control Flow support for pre EG gen 
llvm-svn: 179020
 2013-04-08 13:05:49 +00:00
Tom Stellard 754f80ff3a R600/SI: Add support for buffer stores v2 
v2:
  - Use the ADDR64 bit

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178931
 2013-04-05 23:31:51 +00:00
Tom Stellard 6db08eb42f R600/SI: Use same names for corresponding MUBUF operands and encoding fields 
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178930
 2013-04-05 23:31:44 +00:00
Tom Stellard 60174bb9ca R600: Add RV670 processor 
This is an R600 GPU with double support.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178929
 2013-04-05 23:31:40 +00:00
Tom Stellard 2f21c7e551 R600/SI: Add processor types for each SI variant 
Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178928
 2013-04-05 23:31:35 +00:00
Tom Stellard edbf1eb42b R600/SI: Avoid generating S_MOVs with 64-bit immediates v2 
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate.  Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.

v2:
  - Clean up logic

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 178927
 2013-04-05 23:31:20 +00:00
Vincent Lejeune bcbb13d691 R600: Use a mask for offsets when encoding instructions 
llvm-svn: 178763
 2013-04-04 14:00:09 +00:00
Vincent Lejeune 8e377fdba6 R600: Fix wrong address when substituting ENDIF 
llvm-svn: 178762
 2013-04-04 14:00:03 +00:00
Vincent Lejeune c44fa99719 R600: Take export into account when computing cf address 
llvm-svn: 178761
 2013-04-04 13:59:59 +00:00
Vincent Lejeune c3d3f9b66e R600: Fix last ALU of a clause being emitted in a separate clause 
llvm-svn: 178675
 2013-04-03 18:24:47 +00:00
Vincent Lejeune 80031d9fc4 R600: Factorize maximum alu per clause in a single location 
llvm-svn: 178667
 2013-04-03 16:49:34 +00:00
Vincent Lejeune b6d6c0d458 R600: Simplify data structure and add DEBUG to R600ControlFlowFinalizer 
llvm-svn: 178665
 2013-04-03 16:24:09 +00:00
Vincent Lejeune 9931298b30 R600: Consider KILLGT as an ALU instruction 
Mesa does not override llvm behavior wrt KILLGT anymore so llvm
has to handle KILLGT on its own.

llvm-svn: 178664
 2013-04-03 16:24:04 +00:00
NAKAMURA Takumi fd98f7f2b6 Target/R600: Fix CMake build to add missing files. 
llvm-svn: 178508
 2013-04-01 22:05:58 +00:00
Vincent Lejeune bfaa63a6db R600: Add support for native control flow 
llvm-svn: 178505
 2013-04-01 21:48:05 +00:00