31457d54f7
[X86][XOP] Enable commutation for XOP instructions
...
Patch to allow XOP instructions (integer comparison and integer multiply-add) to be commuted. The comparison instructions sometimes require the compare mode to be flipped but the remaining instructions can use default commutation modes.
This patch also sets the SSE domains of all the XOP instructions.
Differential Revision: http://reviews.llvm.org/D7646
llvm-svn: 229267
2015-02-14 22:40:46 +00:00
916708f152
[X86] Add support for parsing and printing the mnemonic aliases for the XOP VPCOM instructions.
...
llvm-svn: 229078
2015-02-13 07:42:25 +00:00
68ab0465a0
[X86] Remove the remaining uses of memop from AVX and AVX2 instruction patterns. AVX and AVX2 can handle unaligned loads being folded so we can just use 'load'
...
llvm-svn: 228551
2015-02-08 22:38:25 +00:00
d402df3ce8
Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field in TSFlags.
...
llvm-svn: 200624
2014-02-02 07:08:01 +00:00
9e3e38ae3f
Add XOP disassembler support. Fixes PR13933.
...
llvm-svn: 191874
2013-10-03 05:17:48 +00:00
a73be890a1
Add explicit VEX_L tags to all 256-bit instructions. This will allow us to remove code from the code emitters that examined operands to set the L-bit.
...
llvm-svn: 164202
2012-09-19 06:06:34 +00:00
71dc02d659
Fix intrinsics for XOP frczss/sd instructions. These instructions only take one source register and zero the upper bits of the destination rather than preserving them.
...
llvm-svn: 158396
2012-06-13 07:18:53 +00:00
7afe343be5
Add intrinsics for immediate form of XOP vprot instructions. Use i128mem instead of f128mem for integer XOP instructions.
...
llvm-svn: 158291
2012-06-10 07:31:56 +00:00
a54893c662
Use XOP vpcom intrinsics in patterns instead of a target specific SDNode type. Remove the custom lowering code that selected the SDNode type.
...
llvm-svn: 158279
2012-06-09 17:02:24 +00:00
e1d619691b
some comment fix for X86 and ARM
...
llvm-svn: 150902
2012-02-19 02:03:36 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
...
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
4daa67483d
Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file.
...
llvm-svn: 149795
2012-02-05 00:55:56 +00:00
ca29bcfc10
Move some XOP patterns into instruction definition. Replae VPCMOV intrinsic patterns with custom lowering to a target specific nodes.
...
llvm-svn: 149216
2012-01-30 01:10:15 +00:00
86e44bc829
Add HasXOP predicate check covering a bunch of XOP intrinsic patterns.
...
llvm-svn: 149054
2012-01-26 07:51:55 +00:00
21f83d9f36
Add XOP Intrinsics and tests
...
llvm-svn: 147949
2012-01-11 15:20:20 +00:00
2ba766ae84
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
...
llvm-svn: 147368
2011-12-30 06:23:39 +00:00
cd93de93fa
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
...
llvm-svn: 147366
2011-12-30 04:48:54 +00:00
7c0face455
XOP instructions and encoding tests.
...
llvm-svn: 146407
2011-12-12 19:37:49 +00:00
Simon Pilgrim