67fc141db5
Match TargetInstrInfo changes.
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llvm-svn: 32098
2006-12-01 21:52:58 +00:00
20350c4025
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
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of opcode and number of operands.
llvm-svn: 31947
2006-11-27 23:37:22 +00:00
de5fa025ab
Hopefully a good crack at making debugging work on intel -disable-fp-elim.
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llvm-svn: 31830
2006-11-17 21:19:15 +00:00
572dc9cb4e
Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64.
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llvm-svn: 31795
2006-11-16 23:33:25 +00:00
dc2c8748a7
Properly transfer kill / dead info.
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llvm-svn: 31765
2006-11-15 20:58:11 +00:00
dbd3d294e6
Matches MachineInstr changes.
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llvm-svn: 31712
2006-11-13 23:36:35 +00:00
286357480c
Fix a potential bug.
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llvm-svn: 31634
2006-11-10 09:13:37 +00:00
8c9c6d71ed
Add implicit def / use operands to MachineInstr.
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llvm-svn: 31633
2006-11-10 08:43:01 +00:00
14140059f0
Use TargetInstrInfo::getNumOperands() instead of MachineInstr::getNumOperands(). In preparation for implicit reg def/use changes.
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llvm-svn: 31616
2006-11-10 01:28:43 +00:00
1698c2999c
Remove M_2_ADDR_FLAG.
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llvm-svn: 31583
2006-11-09 02:22:54 +00:00
94b29e9e91
Dead code.
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llvm-svn: 31405
2006-11-03 02:08:41 +00:00
1da0ab2f58
Delete dead code; fix 80 col violations.
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llvm-svn: 30583
2006-09-22 21:43:59 +00:00
6f7072c66a
Added some eye-candy for Subtarget type checking
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Added X86 StdCall & FastCall calling conventions. Codegen will follow.
llvm-svn: 30446
2006-09-17 20:25:45 +00:00
de33f66286
Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndex
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in addition to immediate operands.
llvm-svn: 30205
2006-09-08 21:08:13 +00:00
11b0a5dbd4
Committing X86-64 support.
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llvm-svn: 30177
2006-09-08 06:48:29 +00:00
1b7f09cdf7
Some notes on better load folding we could do
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llvm-svn: 30155
2006-09-07 20:32:01 +00:00
7a150d3113
Fix a few dejagnu failures. e.g. fast-cc-merge-stack-adj.ll
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llvm-svn: 30113
2006-09-05 08:32:49 +00:00
af23f9b5f6
Completely eliminate def&use operands. Now a register operand is EITHER a
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def operand or a use operand.
llvm-svn: 30109
2006-09-05 02:31:13 +00:00
13a5dcddce
Fix a long-standing wart in the code generator: two-address instruction lowering
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actually *removes* one of the operands, instead of just assigning both operands
the same register. This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.
Changing this also gets rid of a bunch of hacky code in various places.
This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.
llvm-svn: 30108
2006-09-05 02:12:02 +00:00
60f1eecd3a
Constify some methods. Patch provided by Anton Vayvod, thanks!
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llvm-svn: 29756
2006-08-17 22:00:08 +00:00
f98bc5288e
Missing a space.
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llvm-svn: 29233
2006-07-20 22:52:28 +00:00
7c860afec6
Tidy up a few things.
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llvm-svn: 29213
2006-07-19 19:32:06 +00:00
18debc21db
Reduce size of routine. Shrinks .o by 37%.
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llvm-svn: 29210
2006-07-19 17:53:32 +00:00
fa9e60895b
Add shift and rotate by 1 instructions / patterns.
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llvm-svn: 28980
2006-06-29 00:36:51 +00:00
17ca732b6a
Cygwin support: use _alloca to allocate stack if > 4k. Patch by Anton Korobeynikov.
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llvm-svn: 28764
2006-06-13 05:14:44 +00:00
dc614c193e
Added X86FunctionInfo subclass of MachineFunction to record whether the
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function that is being lowered is forced to use FP. Currently this is only
true for main() / Cygwin.
llvm-svn: 28703
2006-06-06 23:30:24 +00:00
e8a42360c5
Cygwin support. Patch by Anton Korobeynikov!
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llvm-svn: 28672
2006-06-02 22:38:37 +00:00
25e44e008d
Rename instructions for consistency sake.
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llvm-svn: 28594
2006-05-31 19:00:07 +00:00
305c49579c
getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd.
...
llvm-svn: 28378
2006-05-18 00:12:58 +00:00
9fee442e63
X86 integer register classes naming changes. Make them consistent with FP, vector classes.
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llvm-svn: 28324
2006-05-16 07:21:53 +00:00
b19ce6c810
More coverity fixes
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llvm-svn: 28266
2006-05-12 21:14:20 +00:00
9733bde74c
Fixing truncate. Previously we were emitting truncate from r16 to r8 as
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movw. That is we promote the destination operand to r16. So
%CH = TRUNC_R16_R8 %BP
is emitted as
movw %bp, %cx.
This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.
We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.
Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.
llvm-svn: 28164
2006-05-08 08:01:26 +00:00
ddb6cc1d8e
Better implementation of truncate. ISel matches it to a pseudo instruction
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that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.
llvm-svn: 28119
2006-05-05 05:40:20 +00:00
469647bf38
Remove and simplify some more machineinstr/machineoperand stuff.
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llvm-svn: 28105
2006-05-04 18:16:01 +00:00
10d6341618
Move some methods out of MachineInstr into MachineOperand
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llvm-svn: 28102
2006-05-04 17:52:23 +00:00
fef7a2d0f5
There shalt be only one "immediate" operand type!
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llvm-svn: 28099
2006-05-04 17:21:20 +00:00
940cc978ef
Remove a bunch more SparcV9 specific stuff
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llvm-svn: 28093
2006-05-04 01:15:02 +00:00
f0157cb0bc
Use movaps instead of movapd for spill / restore.
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llvm-svn: 28005
2006-04-28 02:23:35 +00:00
ab0ee6340c
MakeMIInst() should handle jump table index operands.
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llvm-svn: 27955
2006-04-24 05:37:35 +00:00
3823aa1d0f
- PEXTRW cannot take a memory location as its first source operand.
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- PINSRWrmi encoding bug.
llvm-svn: 27818
2006-04-18 21:59:43 +00:00
43f4ef4ffb
SHUFP{S|D}, PSHUF* encoding bugs. Left out the mask immediate operand.
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llvm-svn: 27817
2006-04-18 21:56:36 +00:00
09e36ef710
Encoding bug: CMPPSrmi, CMPPDrmi dropped operand 2 (condtion immediate).
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llvm-svn: 27815
2006-04-18 21:31:08 +00:00
bf0d13c54f
Incorrect foldMemoryOperand entries
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llvm-svn: 27763
2006-04-17 18:06:12 +00:00
685ddd8152
Can't fold loads into alias vector SSE ops used for scalar operation. The load
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address has to be 16-byte aligned but the values aren't spilled to 128-bit
locations.
llvm-svn: 27732
2006-04-16 06:58:19 +00:00
0ba896c75b
Added SSE (and other) entries to foldMemoryOperand().
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llvm-svn: 27716
2006-04-14 23:33:27 +00:00
e349d01acf
We were not adjusting the frame size to ensure proper alignment when alloca /
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vla are present in the function. This causes a crash when a leaf function
allocates space on the stack used to store / load with 128-bit SSE
instructions.
llvm-svn: 27698
2006-04-14 07:26:43 +00:00
c9ed8e4c1a
Use movaps to do VR128 reg-to-reg copies for now. It's shorter and available for SSE1.
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llvm-svn: 27554
2006-04-10 07:21:31 +00:00
2d7298c362
Foundation for call frame information.
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llvm-svn: 27491
2006-04-07 16:34:46 +00:00
8f3b6b8d8a
Minor fixes + naming changes.
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llvm-svn: 27410
2006-04-04 19:12:30 +00:00
d1aa1638c6
Expose base register for DwarfWriter. Refactor code accordingly.
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llvm-svn: 27225
2006-03-28 13:48:33 +00:00
Evan Cheng