Commit Graph

584 Commits

Author SHA1 Message Date
Bill Schmidt 8ff672d397 [PowerPC] Enable vec_perm for long long and double vector types for VSX
VSX makes the "vector long long" and "vector double" types available.
This patch enables the vec_perm interface for these types.  The same
builtin is generated regardless of the specified type, so no
additional work or testing is needed in the back end.  Tests are added
to ensure this builtin is generated by the front end.

llvm-svn: 221988
2014-11-14 13:10:13 +00:00
Bill Schmidt cee13a2712 [PowerPC] Add VSX builtins for vec_div
This patch adds builtin support for xvdivdp and xvdivsp, along with a
new test case.  The builtins are accessed using vec_div in altivec.h.
Builtins are listed (mostly) alphabetically there, so inserting these
changed the line numbers for deprecation warnings tested in
test/Headers/altivec-intrin.c.

There is a companion patch for LLVM.

llvm-svn: 221984
2014-11-14 12:10:51 +00:00
Bill Schmidt 9ec8cea02b [PowerPC] Add vec_vsx_ld and vec_vsx_st intrinsics
This patch enables the vec_vsx_ld and vec_vsx_st intrinsics for
PowerPC, which provide programmer access to the lxvd2x, lxvw4x,
stxvd2x, and stxvw4x instructions.

New code in altivec.h defines these in terms of new builtins, which
are themselves defined in BuiltinsPPC.def.  The builtins are converted
to LLVM intrinsics in CGBuiltin.cpp.  Additional code is added to
builtins-ppc-vsx.c to verify the correct generation of the intrinsics.

Note that I moved the other VSX builtins so all VSX builtins will be
alphabetical in their own section in BuiltinsPPC.def.

There is a companion patch for LLVM.

llvm-svn: 221768
2014-11-12 04:19:56 +00:00
Craig Topper 8c7f251e98 Add FSGSBASE intrinsics to x86 intrinsic headers.
llvm-svn: 221130
2014-11-03 06:51:41 +00:00
Craig Topper 554797f255 Remove definitions from Intrin.h that already exist in one of the other x86 intrinsic headers. Add a run line with Broadwell as the cpu type to ms-intrin.cpp test to catch some of these in the future.
llvm-svn: 221127
2014-11-03 04:19:58 +00:00
Craig Topper e1c664b136 Add _lzcnt_u32 and _lzcnt_u64 to lzcntintrin.h to match Intel documentation names for these intrinsics.
llvm-svn: 221066
2014-11-01 22:50:57 +00:00
Craig Topper a52e0d7cc0 Avoid undefined behavior in the x86 bmi header file by explicitly checking for 0 before calling __builtin_ctz. Without this the optimizers may take advantage of the undefined behavior and produce incorrect results. LLVM itself still needs to be taught to merge the zero check into the llvm.cttz with defined zero behavior.
llvm-svn: 221065
2014-11-01 22:50:54 +00:00
Craig Topper 3ca55d9c41 Avoid undefined behavior in the x86 lzcnt header file by explicitly checking for 0 before calling __builtin_clz. Without this the optimizers may take advantage of the undefined behavior and produce incorrect results. LLVM itself still needs to be taught to merge the zero check into the llvm.ctlz with defined zero behavior.
llvm-svn: 221064
2014-11-01 22:25:23 +00:00
Bill Schmidt 691e01d94e [PowerPC] Initial VSX intrinsic support, with min/max for vector double
Now that we have initial support for VSX, we can begin adding
intrinsics for programmer access to VSX instructions.  This patch
performs the necessary enablement in the front end, and tests it by
implementing intrinsics for minimum and maximum using the vector
double data type.

The main change in the front end is to no longer disallow "vector" and
"double" in the same declaration (lib/Sema/DeclSpec.cpp), but "vector"
and "long double" must still be disallowed.  The new intrinsics are
accessed via vec_max and vec_min with changes in
lib/Headers/altivec.h.  Note that for v4f32, we already access
corresponding VMX builtins, but with VSX enabled we should use the
forms that allow all 64 vector registers.

The new built-ins are defined in include/clang/Basic/BuiltinsPPC.def.

I've added a new test in test/CodeGen/builtins-ppc-vsx.c that is
similar to, but much smaller than, builtins-ppc-altivec.c.  This
allows us to test VSX IR generation without duplicating CHECK lines
for the existing bazillion Altivec tests.

Since vector double is now legal when VSX is available, I've modified
the error message, and changed where we test for it and for vector
long double, since the target machine isn't visible in the old place.
This serendipitously removed a not-pertinent warning about 'long'
being deprecated when used with 'vector', when "vector long double" is
encountered and we just want to issue an error.  The existing tests
test/Parser/altivec.c and test/Parser/cxx-altivec.cpp have been
updated accordingly, and I've added test/Parser/vsx.c to verify that
"vector double" is now legitimate with VSX enabled.

There is a companion patch for LLVM.

llvm-svn: 220989
2014-10-31 19:19:24 +00:00
Saleem Abdulrasool a25fbef088 CodeGen: add __readfsdword builtin
The Windows NT SDK uses __readfsdword and declares it as a compiler provided
builtin (#pragma intrinsic(__readfsword).  Because intrin.h is not referenced
by winnt.h, it is not possible to provide an out-of-line definition for the
intrinsic.  Provide a proper compiler builtin definition.

llvm-svn: 220859
2014-10-29 16:35:41 +00:00
NAKAMURA Takumi a267847538 <float.h>: Don't seek #include_next if -ffreestanding for targeting mingw.
llvm-svn: 220356
2014-10-22 01:25:49 +00:00
Hans Wennborg 818514b718 vadefs.h: be even more conservative and only define the macros if already defined
llvm-svn: 219745
2014-10-14 23:20:25 +00:00
Hans Wennborg 752b789e7b Sort files list in lib/Headers/CMakeLists.txt
majnemer pointed out that vadefs.h was added in the wrong place. Might
as well sort the rest too.

llvm-svn: 219743
2014-10-14 23:15:43 +00:00
Hans Wennborg adfd7f6ef4 MS Compat: interpose vadefs.h to fix definitions of _crt_va_{start,end,arg} (PR21247)
Differential revision: http://reviews.llvm.org/D5784

llvm-svn: 219740
2014-10-14 22:35:42 +00:00
Robert Khasanov 33e7685b2a Added new headers to CMakeLists.txt.
Fix for rev219319

llvm-svn: 219325
2014-10-08 17:37:51 +00:00
Robert Khasanov b9f3a911c9 [AVX512] Added VPCMPEQ intrinisics to headers.
Added tests.

Patch by Maxim Blumenthal <maxim.blumenthal@intel.com>

llvm-svn: 219319
2014-10-08 17:18:13 +00:00
Bill Schmidt cad3a5f7d4 [PATCH][Power] Fix (and deprecate) vec_lvsl and vec_lvsr for little endian
The use of the vec_lvsl and vec_lvsr interfaces are discouraged for
little endian targets since Power8 hardware is a minimum requirement,
and Power8 provides reasonable performance for unaligned vector loads
and stores.  Up till now we have not provided "correct" (i.e., big-
endian-compatible) code generation for these interfaces, as to do so
produces poorly performing code.  However, this has become the source
of too many questions.

With this patch, LLVM will now produce compatible code for these
interfaces, but will also produce a deprecation warning message for
PPC64LE when one of them is used.  This should make the porting direction
clearer to programmers.  A similar patch has recently been committed to
GCC.

This patch includes a test for the warning message.  There is a companion
patch that adds two unit tests to projects/test-suite.

llvm-svn: 219137
2014-10-06 19:02:20 +00:00
Hal Finkel 6970ac8b0a Add an implementation of C11's stdatomic.h
Adds a Clang-specific implementation of C11's stdatomic.h header. On systems,
such as FreeBSD, where a stdatomic.h header is already provided, we defer to
that header instead (using our __has_include_next technology). Otherwise, we
provide an implementation in terms of our __c11_atomic_* intrinsics (that were
created for this purpose).

C11 7.1.4p1 requires function declarations for atomic_thread_fence,
atomic_signal_fence, atomic_flag_test_and_set,
atomic_flag_test_and_set_explicit, and atomic_flag_clear, and requires that
they have external linkage. Accordingly, we provide these declarations, but if
a user elides the shadowing macros and uses them, then they must have a libc
(or similar) that actually provides definitions.

atomic_flag is implemented using _Bool as the underlying type. This is
consistent with the implementation provided by FreeBSD and also GCC 4.9 (at
least when __GCC_ATOMIC_TEST_AND_SET_TRUEVAL == 1).

Patch by Richard Smith (rebased and slightly edited by me -- Richard said I
should drive at this point).

llvm-svn: 218957
2014-10-03 04:29:40 +00:00
Richard Smith ef99e4d88a Fix interaction of max_align_t and modules.
When building with modules enabled, we were defining max_align_t as a typedef
for a different anonymous struct type each time it was included, resulting in
an error if <stddef.h> is not covered by a module map and is included more than
once in the same modules-enabled compilation of C11 or C++11 code.

llvm-svn: 218931
2014-10-03 00:31:35 +00:00
Joerg Sonnenberger 2960178a77 Fix trailing commas in AMD define.
llvm-svn: 218825
2014-10-01 21:22:17 +00:00
Joerg Sonnenberger e028e05a7e Add the various signature macros.
llvm-svn: 218824
2014-10-01 21:21:42 +00:00
Joerg Sonnenberger cf0740454d Rename bit_RDRAND to bit_RDRND to match GCC's version of this header.
llvm-svn: 218823
2014-10-01 21:21:16 +00:00
Robert Khasanov ea13042cf2 [x86] Fixed argument types in intrinsics:
_addcarryx_u64
_addcarry_u64
_subborrow_u64

Thanks Pasi Parviainen for notice.

llvm-svn: 218376
2014-09-24 06:45:23 +00:00
Akira Hatanaka 416efb5f90 Fix bugs in cpuid.h.
This commit makes two changes:

- Remove the push and pop instructions that were saving and restoring %ebx
  before and after cpuid in 32-bit pic mode. We were doing this to ensure we
  don't lose the GOT address in pic register %ebx, but this isn't necessary
  because the GOT address is kept in a virtual register.

- In 64-bit mode, preserve base register %rbx around cpuid.

This fixes PR20311 and rdar://problem/17686779.

llvm-svn: 218173
2014-09-20 01:31:09 +00:00
Robert Khasanov 2c589bcc5e [x86] Add _addcarry_u{32|64} and _subborrow_u{32|64}.
They are added to adxintrin.h but outside __ADX__ block.
These intrinics generates adc and sbb correspondingly that were available before ADX
            

llvm-svn: 218118
2014-09-19 10:29:22 +00:00
Robert Khasanov 83c419b349 [x86] Added _addcarryx_u32, _addcarryx_u64 intrinsics
llvm-svn: 218117
2014-09-19 10:17:06 +00:00
Yi Kong a8833f0c28 arm_acle: Fix error in ROR implementation
The logic in calculating the rotate amount was flawed.

Thanks Pasi Parviainen for pointing out!

llvm-svn: 216669
2014-08-28 15:25:52 +00:00
Yi Kong 623393f31e arm_acle: Implement data processing intrinsics
Summary:
ACLE 2.0 section 9.2 defines the following "miscellaneous data processing intrinsics": `__clz`, `__cls`, `__ror`, `__rev`, `__rev16`, `__revsh` and `__rbit`.

`__clz` has already been implemented in the arm_acle.h header file. The rest are not supported yet. This patch completes ACLE data processing intrinsics.

Reviewers: t.p.northover, rengolin

Reviewed By: rengolin

Subscribers: aemerson, mroth, llvm-commits

Differential Revision: http://reviews.llvm.org/D4983

llvm-svn: 216658
2014-08-28 09:44:07 +00:00
Yi Kong 6891746cd8 arm_acle: Add mappings for dbg intrinsic
This completes all ACLE hint intrinsics.

llvm-svn: 216453
2014-08-26 12:48:11 +00:00
Yi Kong 0705e0065e arm_acle: Implement swap intrinsic
Insert the LDREX/STREX instruction sequence specified in ARM ACLE 2.0,
as SWP instruction is deprecated since ARMv6.

llvm-svn: 216446
2014-08-26 09:50:54 +00:00
Yi Kong 70cf4c626e arm_acle.h: Small cleanup
Since __SIZEOF_LONG_LONG__ is always defined as 8 on ARM targets,
there's no point in checking this. NFC.

Patch by Moritz Roth.

llvm-svn: 215697
2014-08-15 08:53:22 +00:00
Adam Nemet 2278fcbf0c [AVX512] Add FMA intrinsics
Part of <rdar://problem/17688758>

llvm-svn: 215666
2014-08-14 17:17:57 +00:00
Yi Kong 45a09319bf ARM: Add mappings for ACLE prefetch intrinsics
Implement __pld, __pldx, __pli and __plix builtin intrinsics as specified in
ARM ACLE 2.0.

llvm-svn: 215599
2014-08-13 23:20:15 +00:00
Adam Nemet 4abc07cb75 [AVX512] Add intrinsics for FP scalar broadcasts
Similar approach to the set1 intrinsics is used: implement in terms of vector
initializers and then ensure with an LLVM test that a broadcast is generated
at the end.

Part of <rdar://problem/17688758>

llvm-svn: 215486
2014-08-13 00:29:01 +00:00
Adam Nemet 5bf7baa938 [AVX512] Add intrinsic for valignd/q
Note that similar to palingr, we could further optimize these to emit
shufflevector when the shift count is <=64.  This however does not
change the overall design that unlike palignr we would still need the LLVM
intrinsic corresponding to this intruction to handle the >64 cases.  (palignr
uses the psrldq intrinsic in this case.)

llvm-svn: 214891
2014-08-05 17:28:23 +00:00
Bill Schmidt ccbe0a8022 [PPC64LE] Fix wrong IR for vec_sld and vec_vsldoi
My original LE implementation of the vsldoi instruction, with its
altivec.h interfaces vec_sld and vec_vsldoi, produces incorrect
shufflevector operations in the LLVM IR.  Correct code is generated
because the back end handles the incorrect shufflevector in a
consistent manner.

This patch and a companion patch for LLVM correct this problem by
removing the fixup from altivec.h and the corresponding fixup from the
PowerPC back end.  Several test cases are also modified to reflect the
now-correct LLVM IR.

The vec_sums and vec_vsumsws interfaces in altivec.h are also fixed,
because they used vec_perm calls intended to be recognized as vsldoi
instructions.  These vec_perm calls are now replaced with code that
more clearly shows the intent of the transformation.

llvm-svn: 214801
2014-08-04 23:21:26 +00:00
Adam Nemet da82bcc4dd [AVX512] Add unaligned FP load intrinsics
Part of <rdar://problem/17688758>

llvm-svn: 214380
2014-07-31 04:00:39 +00:00
Adam Nemet 2db1d2fb32 [AVX512] Add intrinsic for knot
Part of <rdar://problem/17688758>

llvm-svn: 214316
2014-07-30 16:51:27 +00:00
Adam Nemet c871ff95f3 [AVX512] Add some of the FP cast intrinsics
Part of <rdar://problem/17688758>

llvm-svn: 214315
2014-07-30 16:51:24 +00:00
Adam Nemet f42e7a274a [AVX512] Add set1 intrinsics
(Dropped the byte and word variants from the patch.  Turns out these are not
part of AVX512F but only AVX512BW/VL.)

Part of <rdar://problem/17688758>

llvm-svn: 214314
2014-07-30 16:51:22 +00:00
Joerg Sonnenberger 3d9478cf3a Change __INTx_TYPE__ to be always signed. This changes the value for
char-based types from "char" to "signed char". Adjust stdint.h to use
__INTx_TYPE__ directly without prefixing it with signed and to use
__UINTx_TYPE__ for unsigned ones.

The value of __INTx_TYPE__ now matches GCC.

llvm-svn: 214119
2014-07-28 21:06:22 +00:00
Adam Nemet fce1ad0b99 [AVX512] Add non-masking FP store intrinsics
Part of <rdar://problem/17688758>

llvm-svn: 214099
2014-07-28 17:14:45 +00:00
Adam Nemet a3ebe6214b [AVX512] Add FP add/sub/mul intrinsics
Part of <rdar://problem/17688758>

llvm-svn: 214098
2014-07-28 17:14:42 +00:00
Adam Nemet 0d5bb5530d [AVX512] Reorder functions in avx512fintrin.h
There is no functional change here.

The idea is to have a similar order and categories of functions that we have
in avxintrin.h.

llvm-svn: 214097
2014-07-28 17:14:40 +00:00
Adam Nemet 9a3ea60a2c [AVX512] Bring the formatting of avx512fintrin.h closer to avxintrin.h
llvm-svn: 214096
2014-07-28 17:14:38 +00:00
Yi Kong cd08139865 Add module map entry for ARM ACLE header file
llvm-svn: 213731
2014-07-23 09:00:21 +00:00
Elena Demikhovsky bd1a49bf81 AVX-512: I added new headers to makefiles. It should resolve tests fail.
If it will not, I'm reverting the both commits.

llvm-svn: 213645
2014-07-22 12:08:25 +00:00
Elena Demikhovsky fcc6df310d AVX-512: Added intrinsics to clang.
The set is small, that what I have right now.
Everybody is welcome to add more.

llvm-svn: 213641
2014-07-22 11:31:39 +00:00
Viktor Kutuzov 99400a5a34 Revert D3908 due to issues on Mac platforms
llvm-svn: 213450
2014-07-19 05:58:38 +00:00
Yi Kong 28d7b02687 ARM: Add ACLE memory barrier intrinsic mapping
llvm-svn: 213261
2014-07-17 12:45:17 +00:00