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23445 Commits

Author SHA1 Message Date
Evan Cheng 7055878170 Add v4i32 <-> v4f32 bitconvert patterns. 
llvm-svn: 26969
 2006-03-23 02:36:37 +00:00
Evan Cheng eb0ce0c547 Allow result node to be a simple leaf node. This enable bitconvert patterns 
like this:
def : Pat<(v4i32 (bitconvert (v4f32 VR128:$src))), (v4i32 VR128:$src)>;

llvm-svn: 26968
 2006-03-23 02:35:32 +00:00
Evan Cheng b9b0550dc6 Add 128-bit integer vector load and add (for testing). 
llvm-svn: 26967
 2006-03-23 01:57:24 +00:00
Nate Begeman fb6e02931c Add support for 8 bit immediates with 16/32 bit cmp instructions 
llvm-svn: 26966
 2006-03-23 01:29:48 +00:00
Chris Lattner b893d04a67 Fix a typo 
llvm-svn: 26965
 2006-03-22 22:20:49 +00:00
Evan Cheng 021bb7c956 Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do 
64-bit vector shuffle.

llvm-svn: 26964
 2006-03-22 22:07:06 +00:00
Evan Cheng 8e4c9ff3dc Replace vector splat test case. 
llvm-svn: 26963
 2006-03-22 21:39:25 +00:00
Evan Cheng fce9a3396b Add a v2f64 splat (using movlhps) test case. 
llvm-svn: 26962
 2006-03-22 20:29:11 +00:00
Chris Lattner 2f4119a608 Implement simple support for vector casting. This can currently only handle 
casts between legal vector types.

llvm-svn: 26961
 2006-03-22 20:09:35 +00:00
Chris Lattner 85633ae8f6 Fix comments 
llvm-svn: 26960
 2006-03-22 20:09:04 +00:00
Evan Cheng ed794cd27b SHUFP* are two address code. 
llvm-svn: 26959
 2006-03-22 20:08:18 +00:00
Chris Lattner 8070c02c2b add a new node 
llvm-svn: 26958
 2006-03-22 19:56:46 +00:00
Evan Cheng bc04722860 Some clean up. 
llvm-svn: 26957
 2006-03-22 19:22:18 +00:00
Evan Cheng d4e1557941 - Supposely movlhps is faster / better than unpcklpd. 
- Don't forget pshufd is only available with sse2.

llvm-svn: 26956
 2006-03-22 19:16:21 +00:00
Chris Lattner 35079019fc test that vspltw is generated for test cases 
llvm-svn: 26955
 2006-03-22 19:12:46 +00:00
Evan Cheng 68ad48bd1a - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954
 2006-03-22 18:59:22 +00:00
Chris Lattner 7d80b4f366 silence a bogus gcc warning 
llvm-svn: 26953
 2006-03-22 17:27:24 +00:00
Reid Spencer 6f682b79af These changes are necessary to support the new llvm-config tool. llvm-config 
is a handy tool for users of LLVM who want to be able to quickly get
information about LLVM's configuration. It is intended to be used in the
command line of other tools. Documentation will be forthcoming in a
subsequent patch.

llvm-svn: 26952
 2006-03-22 15:59:55 +00:00
Evan Cheng 8fdbdf20cd - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
 2006-03-22 08:01:21 +00:00
Chris Lattner e24cf9dfa1 add a note 
llvm-svn: 26950
 2006-03-22 07:33:46 +00:00
Evan Cheng 3617caf526 Fix PSHUF* and SHUF* jit code emission problems 
llvm-svn: 26949
 2006-03-22 07:10:28 +00:00
Chris Lattner 2d52c1b8b9 Eliminate the dependency of ExecutionEngine on the JIT/Interpreter libraries. 
Now you can build a tool with just the JIT or just the interpreter.

llvm-svn: 26946
 2006-03-22 06:07:50 +00:00
Chris Lattner d3a3365904 wrap lines to 80 columns. 
Add static JITCtor/InterpCtor fields

llvm-svn: 26945
 2006-03-22 06:06:37 +00:00
Chris Lattner eccf46950c This has been implemented. Tweak it into another note 
llvm-svn: 26944
 2006-03-22 05:33:23 +00:00
Chris Lattner 4a66d69433 When possible, custom lower 32-bit SINT_TO_FP to this: 
_foo2:
        extsw r2, r3
        std r2, -8(r1)
        lfd f0, -8(r1)
        fcfid f0, f0
        frsp f1, f0
        blr

instead of this:

_foo2:
        lis r2, ha16(LCPI2_0)
        lis r4, 17200
        xoris r3, r3, 32768
        stw r3, -4(r1)
        stw r4, -8(r1)
        lfs f0, lo16(LCPI2_0)(r2)
        lfd f1, -8(r1)
        fsub f0, f1, f0
        frsp f1, f0
        blr

This speeds up Misc/pi from 2.44s->2.09s with LLC and from 3.01->2.18s
with llcbeta (16.7% and 38.1% respectively).

llvm-svn: 26943
 2006-03-22 05:30:33 +00:00
Chris Lattner 77373d1bea Add support for "ri" addressing modes where the immediate is a 14-bit field 
which is shifted left two bits before use.  Instructions like STD use this
addressing mode.

llvm-svn: 26942
 2006-03-22 05:26:03 +00:00
Chris Lattner f5e36c8bc0 fix a warning 
llvm-svn: 26941
 2006-03-22 04:18:34 +00:00
Evan Cheng d097e67544 Some splat and shuffle support. 
llvm-svn: 26940
 2006-03-22 02:53:00 +00:00
Evan Cheng b1d3c64d1f Add a couple more pseudo instructions. 
llvm-svn: 26939
 2006-03-22 02:52:03 +00:00
Chris Lattner 8fa445a89d Endianness does not affect the order of vector fields. This fixes 
SingleSource/UnitTests/Vector/build.c

llvm-svn: 26936
 2006-03-22 01:46:54 +00:00
Chris Lattner 4e7371758f Fix the JIT encoding of the VAForm_1 instructions, including vmaddfp 
llvm-svn: 26935
 2006-03-22 01:44:36 +00:00
Chris Lattner 5be4352124 Enclose some variables in a scope to avoid error with some gcc versions 
llvm-svn: 26934
 2006-03-22 00:12:37 +00:00
Evan Cheng baea59c61c Didn't mean to check this in. No MMX support yet. 
llvm-svn: 26933
 2006-03-21 23:04:23 +00:00
Evan Cheng d5e905d762 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
 2006-03-21 23:01:21 +00:00
Chris Lattner 340a6b5c26 add expand support for extractelement 
llvm-svn: 26931
 2006-03-21 21:02:03 +00:00
Chris Lattner 00f4683bf6 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
llvm-svn: 26930
 2006-03-21 20:51:05 +00:00
Evan Cheng c0af9c6478 Don't forget to promote xform function to an explicit node for def : Pat<> 
patterns.

llvm-svn: 26929
 2006-03-21 20:44:17 +00:00
Chris Lattner 7c0cd8cafc add some trivial support for extractelement. 
llvm-svn: 26928
 2006-03-21 20:44:12 +00:00
Chris Lattner 0d776c5377 add some nodes for extractelement 
llvm-svn: 26927
 2006-03-21 20:43:08 +00:00
Chris Lattner 3a2ae6ad3c Don't emit pseudo instructions! 
llvm-svn: 26926
 2006-03-21 20:19:37 +00:00
Chris Lattner 672a42d731 Add a hacky workaround for crashes due to vectors live across blocks. 
Note that this code won't work for vectors that aren't legal on the
target.  Improvements coming.

llvm-svn: 26925
 2006-03-21 19:20:37 +00:00
Nate Begeman 013127981a Update readme 
llvm-svn: 26924
 2006-03-21 18:58:20 +00:00
Chris Lattner a7afeff875 Add an integer splat test 
llvm-svn: 26923
 2006-03-21 18:27:27 +00:00
Chris Lattner 139eac5b71 Print absolute memory references like this: 
lwz r2, 8(0)
instead of this:
       lwz r2, 8(r0)

This fixes the llc/llc-beta failures on PPC last night.

llvm-svn: 26922
 2006-03-21 17:21:13 +00:00
Evan Cheng 2d819f5fa4 Combine 2 entries 
llvm-svn: 26921
 2006-03-21 07:18:26 +00:00
Evan Cheng aeebc96099 Add a note about x86 register coallescing 
llvm-svn: 26920
 2006-03-21 07:12:57 +00:00
Evan Cheng 1208d9179a - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919
 2006-03-21 07:09:35 +00:00
Chris Lattner 02ad00ad93 minor code simplification 
llvm-svn: 26918
 2006-03-21 06:42:58 +00:00
Chris Lattner bda7310ef7 With Evan's latest tblgen patch, this code is obsolete, thanks Evan! 
llvm-svn: 26917
 2006-03-21 06:37:40 +00:00
Reid Spencer 1e2433f703 Cause the various warnings list to be generated via a <ul> list with 
text enclosed in <tt>. This ensures that (a) the text is in a fixed width
font (to indicated generated text) and (b) the text wraps without causing
the page width to be extended. The main result of this is that the report
will wrap to conform to the window size in which it is displayed instead of
having a very wide length if a warning message is long.

llvm-svn: 26916
 2006-03-21 01:21:39 +00:00