Commit Graph

157684 Commits

Author SHA1 Message Date
Craig Topper da7e78e18c [X86] Rename the rb form of scalar ADD/SUB/MUL/DIV to include _Int since they can only be selected by intrinsics.
llvm-svn: 320283
2017-12-10 04:07:28 +00:00
Craig Topper 4e57776fb2 [X86] Correct the _Int part of more scheduler model instrexes. Put _b in the correct order relative to _Int
llvm-svn: 320282
2017-12-10 03:16:38 +00:00
Craig Topper a2f5528084 [X86] Remove ReadAfterLd from several several rb instructions
This affects CVTSD2SS, FMA, RCP28, RSQRT28, and SQRT scalar instructions

'b' here refers to 'sae' not broadcast. These aren't memory instructions.

llvm-svn: 320281
2017-12-10 03:16:36 +00:00
Craig Topper 29868dcbaa [X86] Fix test case I failed ot update in r320279.
llvm-svn: 320280
2017-12-10 01:27:54 +00:00
Craig Topper 391c6f9507 [X86] Fix bad regular expressions in the scheduler models. Question marks should be outside of multicharacter parenthesized expressions
If the question mark is inside the parentheses it only applies to the single character proceeding it.

I had to make a few additional cleanups to fix some duplicate warnings that were exposed by fixing this.

llvm-svn: 320279
2017-12-10 01:24:08 +00:00
Craig Topper 8ee98d0b51 [X86] Make the _Int part of some instregex sheduler patterns optional
llvm-svn: 320278
2017-12-10 01:24:06 +00:00
Craig Topper 5ffe80103e [X86] Add the commutable floating point min/max pseudo instructions to sandybridge,haswell,broadwell,skylakeclient scheduler models.
llvm-svn: 320277
2017-12-10 01:24:05 +00:00
Simon Pilgrim 6655eef1b4 [X86] Tag PIC setup instruction as jump scheduler class
llvm-svn: 320276
2017-12-10 00:40:37 +00:00
Simon Pilgrim 5d74949e5f [X86] Tag ACQUIRE/RELEASE atomic instructions as microcoded scheduler classes
Note: We may be too pessimistic here and should possibly use something closer to the LOCK arithmetic instructions
llvm-svn: 320275
2017-12-10 00:30:57 +00:00
Simon Pilgrim dcbe723d28 [X86] Tag TLS instructions as system scheduler classes
llvm-svn: 320274
2017-12-10 00:12:57 +00:00
Simon Pilgrim 3508a09455 [X86] Tag ALLOCA/VAARG instructions as system scheduler classes
llvm-svn: 320273
2017-12-10 00:03:16 +00:00
Joel Jones 5cc21e83ce [AArch64] Improve loop unrolling performance on Cavium T99
This patch improves performance on Cavium T99 as shown here (libquantum 0.2.4):

https://docs.google.com/spreadsheets/d/1Lo1o2E1NjrpkwS7DvYYWsiVvPdd93h7KBaqeptMrZPY/edit?usp=sharing

By increasing the LoopMicroOpsBufferSize in the Cavium T99 Scheduler file,
loop unrolling becomes more aggressive. This helps performance on T99.

Test case included.

Patch by Stefan Teleman

Differential Revision: https://reviews.llvm.org/D40695 

llvm-svn: 320272
2017-12-09 23:59:55 +00:00
Simon Pilgrim a42a54258e [InstCombine] Fix SimplifyDemandedUseBits SHL handling (PR35515)
Don't assume that the pattern matched SRL can be cast to an Instruction (might be ConstExpr etc.)

llvm-svn: 320270
2017-12-09 23:42:56 +00:00
Simon Dardis 70dbd5fbd0 Infer lowest bits of an integer Multiply when the low bits of the operands are known
When the lowest bits of the operands to an integer multiply are known, the low bits of the result are deducible.
Code to deduce known-zero bottom bits already existed, but this change improves on that by deducing known-ones.

Patch by: Pedro Ferreira

Reviewers: craig.topper, sanjoy, efriedma

Differential Revision: https://reviews.llvm.org/D34029

llvm-svn: 320269
2017-12-09 23:25:57 +00:00
Craig Topper f4e3044db9 [X86] Use KMOV instructions to zero upper bits of vectors when possible.
llvm-svn: 320268
2017-12-09 23:10:59 +00:00
Craig Topper 5ac75d5628 [X86] Improve lowering of vXi1 insert_subvectors to better utilize (insert_subvector zero, vec, 0) for zeroing upper bits.
This can be better recognized during isel when the producer already zeroed the upper bits.

llvm-svn: 320267
2017-12-09 22:44:42 +00:00
Simon Pilgrim e049038692 [X86] Tag LOCK/REX64/DATA16/DATA32 instruction prefix scheduler classes
llvm-svn: 320266
2017-12-09 21:27:03 +00:00
Simon Pilgrim b2b93f6204 Strip trailing whitespace. NFCI.
llvm-svn: 320265
2017-12-09 20:44:51 +00:00
Simon Pilgrim 7e636cc419 [X86] Tag FS/GS BASE R/W instruction scheduler classes
llvm-svn: 320264
2017-12-09 20:42:27 +00:00
Simon Pilgrim 231fab072f [X86] Tag REP/REPNE prefix instructions as microcoded scheduler classes
llvm-svn: 320263
2017-12-09 20:16:37 +00:00
Simon Pilgrim 2e7314eb2f [X86] Tag missing EH pseudo instruction scheduler classes
llvm-svn: 320262
2017-12-09 20:04:02 +00:00
Simon Pilgrim cb71e72707 [X86] Tag frame pointer XORs instruction scheduler classes
llvm-svn: 320261
2017-12-09 19:56:39 +00:00
Craig Topper 504534514c [X86] Don't use getTargetConstant for all 0s and all 1s mask vector.
llvm-svn: 320260
2017-12-09 19:18:30 +00:00
Adrian Prantl 844f8f21fd Remove duplicate option from documentation.
llvm-svn: 320258
2017-12-09 19:09:59 +00:00
Simon Pilgrim df702104d3 [X86] Tag segment prefixes as NOP instruction scheduling classes
llvm-svn: 320257
2017-12-09 16:58:34 +00:00
Simon Pilgrim d3e21c6b79 [X86][AVX512] Drop a default NoItinerary argument that isn't used any more. NFCI.
Requires re-ordering of AVX512_maskable_custom arguments.

llvm-svn: 320255
2017-12-09 16:20:54 +00:00
Simon Pilgrim a335e1e29d Fix 'enumeral and non-enumeral type in conditional expression' gcc warning. NFCI.
llvm-svn: 320254
2017-12-09 16:19:18 +00:00
Simon Pilgrim 3d0be4f507 Fix signed/unsigned gcc warning. NFCI.
llvm-svn: 320253
2017-12-09 16:04:57 +00:00
Florian Hahn c5bebffe4f [InlineFunction] Set debug loc for call to forward varargs.
Reviewers: aprantl, dblaikie, rnk

Reviewed By: rnk

Subscribers: eraman, llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D40432

llvm-svn: 320252
2017-12-09 14:25:33 +00:00
Craig Topper 6504a8f888 [X86] When inserting into the upper bits of a vXi1 vector, make sure we shift enough bits if we widened the vector.
We may need to widen the vector to make the shifts legal, but if we do that we need to make sure we shift left/right after accounting for the new size. If not we can't guarantee we are shifting in zeros.

The test cases affected actually show cases where we should move the shifts all together, but that's another problem.

llvm-svn: 320248
2017-12-09 08:19:07 +00:00
Dylan McKay ba23343a45 Revert and accidentally committed revert commit
This reverts commit r320245.

llvm-svn: 320247
2017-12-09 08:01:28 +00:00
Dylan McKay f7e8ec1348 [AVR] Fix two CodeGen tests
These were broken because of various printing format changes.

llvm-svn: 320246
2017-12-09 07:51:43 +00:00
Dylan McKay f5422afdf0 Revert "[AVR] Override ParseDirective"
This reverts commit 57c16f9267969ebb09d6448607999b4a9f40c418.

llvm-svn: 320245
2017-12-09 07:51:37 +00:00
Craig Topper b3e14ce90c [X86] Improve lowering of concats of mask vectors to better optimize zero vector inputs.
We were previously using kunpck with zero inputs unnecessarily. And we had cases where we would insert into a zero vector and then insert into larger zero vector incurring two sets of shifts.

llvm-svn: 320244
2017-12-09 07:02:19 +00:00
Dylan McKay 80463fe64d Relax unaligned access assertion when type is byte aligned
Summary:
This relaxes an assertion inside SelectionDAGBuilder which is overly
restrictive on targets which have no concept of alignment (such as AVR).

In these architectures, all types are aligned to 8-bits.

After this, LLVM will only assert that accesses are aligned on targets
which actually require alignment.

This patch follows from a discussion on llvm-dev a few months ago
http://llvm.1065342.n5.nabble.com/llvm-dev-Unaligned-atomic-load-store-td112815.html

Reviewers: bogner, nemanjai, joerg, efriedma

Reviewed By: efriedma

Subscribers: efriedma, cactus, llvm-commits

Differential Revision: https://reviews.llvm.org/D39946

llvm-svn: 320243
2017-12-09 06:45:36 +00:00
Jessica Paquette a249c4f513 [MachineOutliner] Outline calls
The outliner previously would never outline calls. Calls are pretty common in
files, so it makes sense to outline them. In fact, in the LLVM test suite, if
you count the number of instructions that the outliner misses when you outline
calls vs when you don't, it turns out that, on average, around 6% of the
instructions encountered are calls. So, if we outline calls, we can find more
candidates, and thus save some more space.

This commit adds that functionality and updates the mir test to reflect that.

llvm-svn: 320229
2017-12-09 00:43:49 +00:00
Wolfgang Pieb 8b1a175be6 [NFC] Change the string offsets table tests to generate the object on the fly
which enables us to remove the test scripts and object files from the repository.

https://reviews.llvm.org/D40914

llvm-svn: 320227
2017-12-09 00:39:53 +00:00
Kamil Rytarowski 3d3f91e832 Register NetBSD/x86_64 in MemorySanitizer.cpp
Summary:
Reuse the Linux new mapping as it is.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, eugenis, vitalybuka

Reviewed By: vitalybuka

Subscribers: llvm-commits, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D41022

llvm-svn: 320219
2017-12-09 00:32:09 +00:00
Evgeniy Stepanov c667c1f47a Hardware-assisted AddressSanitizer (llvm part).
Summary:
This is LLVM instrumentation for the new HWASan tool. It is basically
a stripped down copy of ASan at this point, w/o stack or global
support. Instrumenation adds a global constructor + runtime callbacks
for every load and store.

HWASan comes with its own IR attribute.

A brief design document can be found in
clang/docs/HardwareAssistedAddressSanitizerDesign.rst (submitted earlier).

Reviewers: kcc, pcc, alekseyshl

Subscribers: srhines, mehdi_amini, mgorny, javed.absar, eraman, llvm-commits, hiraditya

Differential Revision: https://reviews.llvm.org/D40932

llvm-svn: 320217
2017-12-09 00:21:41 +00:00
Paul Robinson 8bd9d6ad83 Fix out-of-order stepping behavior in programs with sunk instructions.
MachineSink attempts to place instructions near the basic blocks where
they are needed.  Once an instruction has been sunk, its location
relative to other instructions no longer is consistent with the
original source code. In order to ensure correct stepping in the
debugger, the debug location for sunk instructions is either merged
with the insertion point or erased if the target successor block is
empty.

Originally submitted as r318679, revised to fix sanitizer failure and
improve testing.

Patch by Matthew Voss!

Differential Revision: https://reviews.llvm.org/D39933

llvm-svn: 320216
2017-12-09 00:17:01 +00:00
Adrian Prantl 01fb31cc89 dwarfdump: Add support for the --diff option.
--diff      Emit the output in a diff-friendly way by omitting offsets and
            addresses.

<rdar://problem/34502625>

llvm-svn: 320214
2017-12-08 23:32:47 +00:00
Craig Topper e29f50da4d [X86][Mips] Remove unused method declaration from the X86 and Mips AsmPrinters.
Both had a declaration of EmitXRayTable, but there is no method defined in either with that name. There is a emitXRayTable in the base class with a lower case 'e' and they both call that.

llvm-svn: 320213
2017-12-08 23:30:03 +00:00
Francis Visoiu Mistrih 440f69c95a [CodeGen] Move printing MO_Immediate operands to MachineOperand::print
Work towards the unification of MIR and debug output by refactoring the
interfaces.

Add support for operand subreg index as an immediate to debug printing
and use ::print in the MIRPrinter.

Differential Review: https://reviews.llvm.org/D40965

llvm-svn: 320209
2017-12-08 22:53:21 +00:00
Duncan P. N. Exon Smith 9b8caf5bd7 Revert part of "Cleanup some GraphTraits iteration code"
This reverts part of r300656, which caused a regression in
propagateMassToSuccessors by counting edges n^2 times, where n is the
number of edges from the source basic block to the same successor basic
block. The result was both incorrect and very slow to compute for large
values of n (e.g. switches with multiple cases that go to the same basic
block).

Patch by Andrew Scheidecker!

llvm-svn: 320208
2017-12-08 22:42:43 +00:00
Richard Smith 8a3adc3abb Avoid constructing an out-of-range value for an enumeration (which results in UB).
llvm-svn: 320206
2017-12-08 22:32:35 +00:00
Abderrazek Zaafrani 5a2583f026 [AArch64] Rename AArch64VecorByElementOpt.cpp into AArch64SIMDInstrOpt.cpp to reflect the recently added features.
The name change is dicsussed in https://reviews.llvm.org/D38196

llvm-svn: 320204
2017-12-08 22:04:13 +00:00
Adrian Prantl d13170174c Generalize llvm::replaceDbgDeclare and actually support the use-case that
is mentioned in the documentation (inserting a deref before the plus_uconst).

llvm-svn: 320203
2017-12-08 21:58:18 +00:00
Vedant Kumar 195dfd10a6 [Debugify] Add a pass to test debug info preservation
The Debugify pass synthesizes debug info for IR. It's paired with a
CheckDebugify pass which determines how much of the original debug info
is preserved. These passes make it easier to create targeted tests for
debug info preservation.

Here is the Debugify algorithm:

  NextLine = 1
  for (Instruction &I : M)
    attach DebugLoc(NextLine++) to I

  NextVar = 1
  for (Instruction &I : M)
    if (canAttachDebugValue(I))
      attach dbg.value(NextVar++) to I

The CheckDebugify pass expects contiguous ranges of DILocations and
DILocalVariables. If it fails to find all of the expected debug info, it
prints a specific error to stderr which can be FileChecked.

This was discussed on llvm-dev in the thread:
"Passes to add/validate synthetic debug info"

Differential Revision: https://reviews.llvm.org/D40512

llvm-svn: 320202
2017-12-08 21:57:28 +00:00
Florian Hahn e5089e2e94 [CodeExtractor] Add debug locations for new call and branch instrs.
Summary:
If a partially inlined function has debug info, we have to add debug
locations to the call instruction calling the outlined function.
We use the debug location of the first instruction in the outlined
function, as the introduced call transfers control to this statement and
there is no other equivalent line in the source code.

We also use the same debug location for the branch instruction added
to jump from artificial entry block for the outlined function, which just
jumps to the first actual basic block of the outlined function.

Reviewers: davide, aprantl, rriddle, dblaikie, danielcdh, wmi

Reviewed By: aprantl, rriddle, danielcdh

Subscribers: eraman, JDevlieghere, llvm-commits

Differential Revision: https://reviews.llvm.org/D40413

llvm-svn: 320199
2017-12-08 21:49:03 +00:00
Dan Gohman 3a762bf9df [WebAssembly] Reapply r319186: "Support bitcasted function addresses with varargs."
This puts the functionality under control of a command-line option which is
off by default to avoid breaking existing setups.

llvm-svn: 320197
2017-12-08 21:27:00 +00:00