6fdea1bda8
Add full bss data support for darwin tls variables.
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llvm-svn: 104414
2010-05-22 00:10:22 +00:00
4a8e6e83dc
Collect variable information during endFunction() instead of beginFunction().
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llvm-svn: 104412
2010-05-22 00:04:14 +00:00
75ed30b593
Add a new section and accessor for TLS data.
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llvm-svn: 104411
2010-05-22 00:00:58 +00:00
61438fe064
Clean up extra whitespace.
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llvm-svn: 104410
2010-05-21 23:53:55 +00:00
53ff992dde
Make this LookAheadLimit, not the uninitialized LookAheadLeft.
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Evan please verify!
llvm-svn: 104408
2010-05-21 23:40:03 +00:00
4dc833c607
add a note
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llvm-svn: 104404
2010-05-21 23:16:21 +00:00
09d47031b1
Expand on comment.
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llvm-svn: 104396
2010-05-21 23:03:53 +00:00
7e7482c80f
Added retl for 32-bit x86 and added retq for 64-bit x86.
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llvm-svn: 104394
2010-05-21 23:01:38 +00:00
0624d5226c
Fix comment and whitespace.
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llvm-svn: 104392
2010-05-21 22:39:11 +00:00
37c529ae68
expand on the llvm ir bitcode dox. Patch by Peter Housel!
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llvm-svn: 104391
2010-05-21 22:20:54 +00:00
2c8bdead9e
Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs.
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llvm-svn: 104385
2010-05-21 21:22:19 +00:00
3dca28d0e2
Fix section attribute name.
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llvm-svn: 104381
2010-05-21 21:08:52 +00:00
51d9ee3ff6
Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements
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so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.
llvm-svn: 104380
2010-05-21 21:05:32 +00:00
3858451e09
- Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs
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that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.
llvm-svn: 104377
2010-05-21 20:53:24 +00:00
7d7f604321
Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction
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reads or writes a register.
This takes partial redefines and undef uses into account.
Don't actually use it yet. That caused miscompiles.
llvm-svn: 104372
2010-05-21 20:02:01 +00:00
1782aae355
Simplify
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llvm-svn: 104338
2010-05-21 18:49:09 +00:00
2b78565842
Previous commit message should refer to 104308.
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llvm-svn: 104337
2010-05-21 18:44:47 +00:00
6361e3e8a2
Fix two bugs in 104348:
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Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.
llvm-svn: 104336
2010-05-21 18:40:15 +00:00
ea91abddfe
added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter
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If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.
llvm-svn: 104334
2010-05-21 18:23:56 +00:00
0735ecfe17
now that fp reg kill insertion stuff happens as a separate
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pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.
The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes. Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross. It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).
Just do the scan on machine phis which is simpler, faster
and more correct. This fixes PR6828.
llvm-svn: 104333
2010-05-21 18:17:54 +00:00
058a207436
Use less evil form of switch stmt.
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llvm-svn: 104331
2010-05-21 18:02:42 +00:00
39a8a43bd8
use continue to reduce nesting.
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llvm-svn: 104330
2010-05-21 18:01:24 +00:00
b7d68a2256
pull a nested loop of this pass out to its own function,
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eliminating the gymnastics around the ContainsFPCode var.
llvm-svn: 104328
2010-05-21 17:57:03 +00:00
fb41aaefeb
modernize this pass a bit, fit in 80 columns.
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llvm-svn: 104326
2010-05-21 17:49:07 +00:00
a81e1cab04
constify accessor.
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llvm-svn: 104325
2010-05-21 17:47:50 +00:00
b4e1687270
Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read."
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This reverts r104322. I think it was causing miscompilations.
llvm-svn: 104323
2010-05-21 17:36:32 +00:00
8e8e090301
Use MachineInstr::readsWritesVirtualRegister to determine if a register is read.
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This correctly handles partial redefines and undef uses.
llvm-svn: 104322
2010-05-21 16:42:30 +00:00
a648c6a757
Teach VirtRegRewriter to handle spilling in instructions that have multiple
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definitions of the virtual register.
This happens when spilling the registers produced by REG_SEQUENCE:
%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0
The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.
llvm-svn: 104321
2010-05-21 16:36:13 +00:00
1f3801062d
If the first definition of a virtual register is a partial redef, add an
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<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.
llvm-svn: 104320
2010-05-21 16:32:16 +00:00
638cdb2db1
Currently, createMachOStreamer() is invoked directly in llvm-mc which
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isn't ideal if we want to be able to use another object file format.
Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.
llvm-svn: 104318
2010-05-21 12:54:43 +00:00
5abb6dd61e
Split out the x86_32 an x86_64 ELF backends as they handle ELF
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differently. This will make adding ELF support easier in the long run.
llvm-svn: 104317
2010-05-21 11:39:07 +00:00
ec9d6faef0
Add support for parsing the ELF .type assembler directive.
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llvm-svn: 104316
2010-05-21 11:36:59 +00:00
d5f0998c6e
Removed scaleNumbering method declaration from LiveInterval (not defined, not used).
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llvm-svn: 104311
2010-05-21 03:04:04 +00:00
b3b9c8ac48
Fix i64->f64 conversion, x86-64, -no-sse. A bit
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tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.
llvm-svn: 104308
2010-05-21 00:52:33 +00:00
34c260458a
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
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llvm-svn: 104307
2010-05-21 00:43:17 +00:00
725211e948
Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid.
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llvm-svn: 104306
2010-05-21 00:42:32 +00:00
e85262d651
Remove dead option.
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llvm-svn: 104303
2010-05-21 00:27:55 +00:00
fbd6c45e06
Simplify.
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llvm-svn: 104302
2010-05-21 00:10:20 +00:00
c120ffe3f6
Fix __crashreport_info__ declaration.
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llvm-svn: 104300
2010-05-20 23:50:19 +00:00
4401f8873c
Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode.
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llvm-svn: 104293
2010-05-20 23:26:43 +00:00
9b48b856ea
DominatorTree.getNode can return null for unreachable blocks.
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llvm-svn: 104290
2010-05-20 22:46:54 +00:00
86110fa2bb
Minor code cleanups.
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llvm-svn: 104287
2010-05-20 22:25:20 +00:00
3a48292204
Print a space after the colon.
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llvm-svn: 104279
2010-05-20 21:11:37 +00:00
6295f2ebb8
Make Solve check its own post-condition, to reduce clutter in the
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top-level LSRInstance logic.
llvm-svn: 104278
2010-05-20 20:59:23 +00:00
a4ca28a3ae
Add comments.
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llvm-svn: 104276
2010-05-20 20:52:00 +00:00
baf2eea6f4
MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq.
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llvm-svn: 104275
2010-05-20 20:36:29 +00:00
0adee9b362
Rename variable. add comment.
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llvm-svn: 104274
2010-05-20 20:35:24 +00:00
927bcaadda
More code cleanups. Use iterators instead of indices when indices
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aren't needed.
llvm-svn: 104273
2010-05-20 20:33:18 +00:00
61655aa2bb
X86: Model i64i32imm properly, as a subclass of all immediates.
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llvm-svn: 104272
2010-05-20 20:20:39 +00:00
6d4c66dc1d
X86: Fix immediate type of FOO64i32 operations.
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llvm-svn: 104271
2010-05-20 20:20:35 +00:00
Eric Christopher