f881d385da
Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.
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llvm-svn: 160941
2012-07-30 02:14:02 +00:00
7e9415220a
Make CVTDQ2PS instruction use SSE2 predicate instead of SSE1. No functional change because there are no patterns in the instructions. Also fix a typo in a comment.
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llvm-svn: 159087
2012-06-23 20:52:45 +00:00
24e3418215
Move CVTPD2DQ to use SSE2 predicate instead of SSE3. Move DQ2PD and PD2DQ to the SSE2 section of the file.
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llvm-svn: 159086
2012-06-23 20:15:42 +00:00
bf2409e8aa
Mark several instructions SSE2 instead of SSE3 as they should be.
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llvm-svn: 158049
2012-06-06 06:45:27 +00:00
79dbb0c6e4
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.
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llvm-svn: 157903
2012-06-03 18:58:46 +00:00
a0396e4583
X86: Rename the CLMUL target feature to PCLMUL.
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It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.
llvm-svn: 157745
2012-05-31 14:34:17 +00:00
09de6ae399
Added X86 Atom latencies to X86InstrMMX.td.
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llvm-svn: 156615
2012-05-11 14:27:12 +00:00
fa3f6cb830
This patch continues the work of adding instruction latencies for X86 Atom,
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by providing the latencies for the instructions in X86InstrFPStack.td.
llvm-svn: 155996
2012-05-02 16:03:35 +00:00
c0cef32b83
Remove HasSSE2 from AES and CLMUL predicates. It's now implied by the HasAES and HasCLMUL predicates.
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llvm-svn: 155890
2012-05-01 05:35:02 +00:00
66a3597a4a
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
b22310fda6
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
ed7aa46366
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
8523b16ff5
Instruction scheduling itinerary for Intel Atom.
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Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
llvm-svn: 149558
2012-02-01 23:20:51 +00:00
eb8f9e9e5b
Instruction selection priority fixes to remove the XMM/XMMInt/orAVX predicates. Another commit will remove orAVX functions from X86SubTarget.
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llvm-svn: 147841
2012-01-10 06:30:56 +00:00
744f6311d3
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
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llvm-svn: 147762
2012-01-09 00:11:29 +00:00
b910984458
Allow CRC32 instructions to be selected when AVX is enabled.
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llvm-svn: 147411
2012-01-01 19:51:58 +00:00
1c064e0a89
Fix sfence, lfence, mfence, and clflush to be able to be selected when AVX is enabled. Fix monitor and mwait to require SSE3 or AVX, previously they worked even if SSE3 was disabled. Make prefetch instructions not set the execution domain since they don't use XMM registers.
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llvm-svn: 147409
2012-01-01 19:40:22 +00:00
cd93de93fa
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
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llvm-svn: 147366
2011-12-30 04:48:54 +00:00
d773607eee
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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llvm-svn: 147353
2011-12-29 20:43:40 +00:00
97f05c5768
Mark non-VEX forms of PCLMUL instructions as requiring SSE2 to be enabled along with CLMUL. That's required for the XMM registers to be valid for integer data. Doesn't change any behavior since the CLMUL instructions don't have patterns yet.
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llvm-svn: 147345
2011-12-29 18:08:36 +00:00
1559123c77
Mark non-VEX forms of AES instructions as requiring SSE2 to be enabled along with AES. Since that's required for the XMM registers to be valid for integer data. Doesn't change any behavior though since you can't use an intrinsic with an illegal type anyway. Just makes it consistent with the VEX forms.
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llvm-svn: 147344
2011-12-29 18:00:08 +00:00
64944090ff
Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586.
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llvm-svn: 146709
2011-12-15 23:46:18 +00:00
7c0face455
XOP instructions and encoding tests.
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llvm-svn: 146407
2011-12-12 19:37:49 +00:00
6dd2488383
XOP encoding bits and logic.
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llvm-svn: 146397
2011-12-12 19:12:26 +00:00
557cda7f1d
Remove hasSSE1orAVX(). It's the same as hasXMM().
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llvm-svn: 146246
2011-12-09 06:32:46 +00:00
4d1a2d449f
Many of the SSE patterns should not be selected when AVX is available. This led to the following code in X86Subtarget.cpp
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if (HasAVX)
X86SSELevel = NoMMXSSE;
This is so patterns that are predicated on hasSSE3, etc. would not be selected when avx is available. Instead, the AVX variant is selected.
However, this breaks instructions which do not have AVX variants.
The right way to fix this is for the SSE but not-AVX patterns to predicate on something like hasSSE3() && !hasAVX().
Then we can take out the hack in X86Subtarget.cpp. Patterns which do not have AVX variants do not need to change.
However, we need to audit all the patterns before we make the change. This patch is workaround that fixes one specific case,
the prefetch instructions. rdar://10538297
llvm-svn: 146163
2011-12-08 19:00:42 +00:00
0f9a1f5e6c
This patch contains support for encoding FMA4 instructions and
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tablegen patterns for scalar FMA4 operations and intrinsic. Also
add tests for vfmaddsd.
Patch by Jan Sjodin
llvm-svn: 145133
2011-11-25 19:33:42 +00:00
f01f1b5cb9
More AVX2 instructions and their intrinsics.
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llvm-svn: 143895
2011-11-06 23:04:08 +00:00
05d1cb98e7
Add more AVX2 instructions and intrinsics.
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llvm-svn: 143861
2011-11-06 06:12:20 +00:00
980d59832a
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
96fa597828
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
aea148c366
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
f18c896337
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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llvm-svn: 141065
2011-10-04 06:30:42 +00:00
123dff0f58
- Handle special scalar_to_vector case: splats. Using a native 128-bit
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shuffle before inserting on a 256-bit vector.
- Add AVX versions of movd/movq instructions
- Introduce a few COPY patterns to match insert_subvector instructions.
This turns a trivial insert_subvector instruction into a register copy,
coalescing the xmm into a ymm and avoid emiting on more instruction.
llvm-svn: 136002
2011-07-25 23:05:25 +00:00
415412e82f
Add assembler/disassembler support for non-AVX pclmulqdq. While I'm here, use proper aliases for the pclmullqlqdq and friends. PR10269.
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llvm-svn: 134424
2011-07-05 18:21:20 +00:00
fc4789da4a
Add support for the VIA PadLock instructions.
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llvm-svn: 128826
2011-04-04 16:58:13 +00:00
cc53d9919f
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
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Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.
llvm-svn: 128822
2011-04-04 15:58:30 +00:00
b60b0bc47e
Enabled disassembler support for AVX instructions
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in the instruction tables and fixed a few bugs that
were causing decode conflicts. Rudimentary tests
are coming up in the next patch.
llvm-svn: 127646
2011-03-15 01:28:15 +00:00
e39062199e
Implement xgetbv and xsetbv.
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Patch by Jai Menon.
llvm-svn: 126165
2011-02-22 00:35:18 +00:00
3a8ae23313
Fix some grammar in comments I noticed.
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llvm-svn: 120416
2010-11-30 09:11:54 +00:00
ed13239dc0
This defaults to GenericDomain.
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llvm-svn: 120415
2010-11-30 09:11:07 +00:00
ef62f57d4f
Implement a PseudoI class and transfer the sse instructions over to use
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it.
llvm-svn: 120412
2010-11-30 08:57:23 +00:00
7ff334687d
fix the !eq operator in tblgen to return a bit instead of an int.
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Use this to make the X86 and ARM targets set isCodeGenOnly=1
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.
llvm-svn: 117862
2010-10-31 19:22:57 +00:00
45270db916
Implement support for the bizarre 3DNow! encoding (which is unlike anything
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else in X86), and add support for pavgusb. This is apparently the
only instruction (other than movsx) that is preventing ffmpeg from building
with clang.
If someone else is interested in banging out the rest of the 3DNow!
instructions, it should be quite easy now.
llvm-svn: 115466
2010-10-03 18:08:05 +00:00
cea0a8d7ae
fix rdar://8444631 - encoder crash on 'enter'
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What a weird instruction.
llvm-svn: 114190
2010-09-17 18:02:29 +00:00
a967c42a3d
Fix comment typos.
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llvm-svn: 112202
2010-08-26 18:08:11 +00:00
f547740d3f
fix PR7465, mishandling of lcall and ljmp: intersegment long
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call and jumps.
llvm-svn: 111496
2010-08-19 01:18:43 +00:00
beb506eeed
minor progress towards fixing PR7465
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llvm-svn: 111494
2010-08-19 01:00:34 +00:00
ea0e05a3ce
Add AVX version of CLMUL instructions
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llvm-svn: 109248
2010-07-23 18:41:12 +00:00
acd9230b1b
Add complete assembler support for FMA3 instructions, with descriptions and encodings taken from the AVX manual
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llvm-svn: 109204
2010-07-23 00:54:35 +00:00
Craig Topper