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13 Commits

Author SHA1 Message Date
Jim Grosbach c3b0427921 Allow MCCodeEmitter access to the target MCRegisterInfo. 
Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

llvm-svn: 156828
 2012-05-15 17:35:52 +00:00
Rafael Espindola 908d2ed14e Move x86 specific bits of the COFF writer to lib/Target/X86. 
llvm-svn: 147231
 2011-12-24 02:14:02 +00:00
Rafael Espindola b264d33854 Move the X86 specific bits of the ELF writer to the Target/X86 directory. 
Other targets will follow shortly.

llvm-svn: 147060
 2011-12-21 17:30:17 +00:00
Craig Topper 6c8879e3ab Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7. 
llvm-svn: 142089
 2011-10-16 00:21:51 +00:00
Evan Cheng 5928e69d20 Rename TargetAsmBackend to MCAsmBackend; rename createAsmBackend to createMCAsmBackend. 
llvm-svn: 136010
 2011-07-25 23:24:55 +00:00
Oscar Fuentes 47d4aaf8ad Unbreak the build. 
llvm-svn: 135949
 2011-07-25 20:13:36 +00:00
Evan Cheng b25310095f More refactoring. 
llvm-svn: 135939
 2011-07-25 19:33:48 +00:00
Evan Cheng 7e763d86ba Refactor X86 target to separate MC code from Target code. 
llvm-svn: 135930
 2011-07-25 18:43:53 +00:00
Evan Cheng d60fa58ba1 Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo down 
to MCRegisterInfo. Also initialize the mapping at construction time.

This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step
towards fixing the layering violation.

llvm-svn: 135424
 2011-07-18 20:57:22 +00:00
Evan Cheng bc153d49b7 Next round of MC refactoring. This patch factor MC table instantiations, MC 
registeration and creation code into XXXMCDesc libraries.

llvm-svn: 135184
 2011-07-14 20:59:42 +00:00
Evan Cheng 4d1ca96bfc Eliminate asm parser's dependency on TargetMachine: 
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
  to generate asm matcher subtarget feature queries. e.g.
  "ModeThumb,FeatureThumb2" is translated to
  "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".

llvm-svn: 134678
 2011-07-08 01:53:10 +00:00
Evan Cheng 13bcc6c1c7 Add Mode64Bit feature and sink it down to MC layer. 
llvm-svn: 134641
 2011-07-07 21:06:52 +00:00
Evan Cheng 3ddfbd325d Rename files for consistency. 
llvm-svn: 134546
 2011-07-06 22:01:53 +00:00