73136dfecc
- Added option -relocation-model to set relocation model. Valid values include static, pic,
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dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.
llvm-svn: 26315
2006-02-22 20:19:42 +00:00
2fa33a989d
Coordinate activities with llvm-gcc4 and dwarf.
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llvm-svn: 26314
2006-02-22 19:02:11 +00:00
9e252e3bcf
Added MMX, SSE1, and SSE2 vector instructions and some simple patterns.
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Fixed some existing bugs (wrong predicates, prefixes) at the same time.
llvm-svn: 26310
2006-02-22 02:26:30 +00:00
7ad77dfc2a
split register class handling from explicit physreg handling.
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llvm-svn: 26308
2006-02-22 00:56:39 +00:00
7bb4696dc3
Updates to match change of getRegForInlineAsmConstraint prototype
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llvm-svn: 26305
2006-02-21 23:11:00 +00:00
d58478161f
One more round of reorg so sabre doesn't freak out. :-)
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llvm-svn: 26303
2006-02-21 20:00:20 +00:00
6fc1162855
A big more cleaning up.
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llvm-svn: 26302
2006-02-21 19:30:30 +00:00
8711b6bff3
Moving things to their proper places.
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llvm-svn: 26301
2006-02-21 19:26:52 +00:00
6e595b9fd8
Split instruction info into multiple files, one for each of x87, MMX, and SSE.
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llvm-svn: 26300
2006-02-21 19:13:53 +00:00
0a08f44704
missed optzn
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llvm-svn: 26299
2006-02-21 18:29:44 +00:00
747cf60696
The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSchedInserter
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instructions are expensive.
llvm-svn: 26298
2006-02-21 18:04:32 +00:00
d57203c0a1
Added separate alias instructions for SSE logical ops that operate on non-packed types.
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llvm-svn: 26297
2006-02-21 02:24:38 +00:00
afffe63fc1
Added MMX and XMM packed integer move instructions, movd and movq.
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llvm-svn: 26296
2006-02-21 01:39:57 +00:00
fa57a0add9
Added SSE2 128-bit integer packed types: V16I8, V8I16, V4I32, and V2I64.
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Added generic vector types: VR64 and VR128.
llvm-svn: 26295
2006-02-21 01:38:21 +00:00
43070b7541
Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit
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packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).
llvm-svn: 26294
2006-02-20 22:34:53 +00:00
4547400ae2
Some updates
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llvm-svn: 26292
2006-02-20 19:58:27 +00:00
d13778eb30
If SSE3 is available, promote FP_TO_UINT i32 to FP_TO_SINT i64 to take
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advantage of fisttpll.
llvm-svn: 26288
2006-02-18 07:26:17 +00:00
983ca89714
Add a fold for add that exchanges it with a constant shift if possible, so
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that the shift may be more easily folded into other operations.
llvm-svn: 26286
2006-02-18 02:43:25 +00:00
70af620709
Added fisttp for fp to int conversion.
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llvm-svn: 26283
2006-02-18 02:36:28 +00:00
06c2e6d1b3
Disable PIC for JIT.
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llvm-svn: 26281
2006-02-18 01:49:25 +00:00
5caed8a231
Jit does not support PIC yet.
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llvm-svn: 26278
2006-02-18 00:57:10 +00:00
5588de9415
x86 / Darwin PIC support.
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llvm-svn: 26273
2006-02-18 00:15:05 +00:00
5f99760ae7
Moved PICEnabled to include/llvm/Target/TargetOptions.h
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llvm-svn: 26272
2006-02-18 00:08:58 +00:00
07a2677e43
unbreak the build
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llvm-svn: 26260
2006-02-17 07:09:27 +00:00
593bea73ba
Unbreak x86 be
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llvm-svn: 26259
2006-02-17 07:01:52 +00:00
5965bd19f8
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
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and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
llvm-svn: 26255
2006-02-17 05:43:56 +00:00
67c21b6c46
add note about div by power of 2
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llvm-svn: 26253
2006-02-17 04:20:13 +00:00
0d62ebd13f
Fix bug noticed by VC++.
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llvm-svn: 26252
2006-02-17 02:12:18 +00:00
3920ce4d8d
Whoops, didn't mean to check this in yet.
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llvm-svn: 26250
2006-02-17 00:56:19 +00:00
4a0dc0c8f6
Add a missing and useful pat frag
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llvm-svn: 26249
2006-02-17 00:51:06 +00:00
b590d3a72b
Remind ourselves to revisit the "pxor vs. xorps/xorpd to clear XMM registers"
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issue. Need to do more experiments.
llvm-svn: 26247
2006-02-17 00:04:28 +00:00
7e5496d5fe
Kill the x86 pattern isel. boom.
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llvm-svn: 26246
2006-02-17 00:03:04 +00:00
db1dbbe8d6
Remove the entry about using movapd for SSE reg-reg moves.
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llvm-svn: 26245
2006-02-17 00:00:58 +00:00
eb7b3380fd
pxor (for FLD0SS) encoding was missing the OpSize prefix.
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llvm-svn: 26244
2006-02-16 23:59:30 +00:00
936cc9fe53
Remove the skeleton target, it doesn't produce useful code and there are
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other small targets that do that can be learned from. They also have
the added advantage of being tested :)
llvm-svn: 26243
2006-02-16 23:14:50 +00:00
24c461b51e
1. Use pxor instead of xoraps / xorapd to clear FR32 / FR64 registers. This
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proves to be worth 20% on Ptrdist/ks. Might be related to dependency
breaking support.
2. Added FsMOVAPSrr and FsMOVAPDrr as aliases to MOVAPSrr and MOVAPDrr. These
are used for FR32 / FR64 reg-to-reg copies.
3. Tell reg-allocator to generate MOVSSrm / MOVSDrm and MOVSSmr / MOVSDmr to
spill / restore FsMOVAPSrr and FsMOVAPDrr.
llvm-svn: 26241
2006-02-16 22:45:17 +00:00
3f99628939
Use movaps / movapd to spill / restore V4F4 / V2F8 registers.
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llvm-svn: 26240
2006-02-16 21:20:26 +00:00
8a77efe4f7
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
01afec2adb
MOVAPSrr and MOVAPDrr instruction format should be MRMSrcReg.
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llvm-svn: 26234
2006-02-16 19:34:41 +00:00
36a2ee299e
distinguish between objects and register names, now we can have stuff
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with names like "f84", "in6" etc etc.
this should fix one or two tests
llvm-svn: 26232
2006-02-16 13:12:57 +00:00
42c01c8d39
If the false case is the current basic block, then this is a self loop.
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We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
llvm-svn: 26231
2006-02-16 08:27:56 +00:00
ae82498e81
Use movaps / movapd (instead of movss / movsd) to do FR32 / FR64 reg to reg
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transfer.
According to the Intel P4 Optimization Manual:
Moves that write a portion of a register can introduce unwanted
dependences. The movsd reg, reg instruction writes only the bottom
64 bits of a register, not to all 128 bits. This introduces a dependence on
the preceding instruction that produces the upper 64 bits (even if those
bits are not longer wanted). The dependence inhibits register renaming,
and thereby reduces parallelism.
Not to mention movaps is shorter than movss.
llvm-svn: 26226
2006-02-16 01:50:02 +00:00
03c1e6f48e
A bit more memset / memcpy optimization.
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Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
llvm-svn: 26224
2006-02-16 00:21:07 +00:00
76a7775ce1
Remove an entry.
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llvm-svn: 26222
2006-02-15 22:14:34 +00:00
6afb5587da
new test
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llvm-svn: 26217
2006-02-15 19:52:06 +00:00
6db414e8de
Sparc actually *DOES* have a directive for emitting zeros. In fact, it requires
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it, because this:
.bss
X:
.byte 0
results in the assembler warning: "initialization in bss segment". Annoying.
llvm-svn: 26204
2006-02-15 07:07:14 +00:00
a9d0b5800a
Fix SingleSource/Regression/C/2004-08-12-InlinerAndAllocas.c on Sparc.
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The ABI specifies that there is a register save area at the bottom of the
stack, which means the actual used pointer needs to be an offset from
the subtracted value.
llvm-svn: 26202
2006-02-15 06:41:34 +00:00
7a6c21ac26
Remove an entry.
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llvm-svn: 26197
2006-02-15 01:56:48 +00:00
2d23c9f1ab
Use .zerofill on x86/darwin.
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llvm-svn: 26196
2006-02-15 01:56:23 +00:00
aacc4c3b4c
cvtsd2ss / cvtss2sd encoding bug.
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llvm-svn: 26193
2006-02-15 00:31:03 +00:00
Evan Cheng