Commit Graph

1804 Commits

Author SHA1 Message Date
Evan Cheng 5457a96b63 Trim more includes.
llvm-svn: 84832
2009-10-22 05:11:00 +00:00
Evan Cheng 344fcd9d61 Trim include.
llvm-svn: 84831
2009-10-22 05:08:49 +00:00
Evan Cheng 0f55e9ce2e Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad.
llvm-svn: 84813
2009-10-22 00:40:00 +00:00
Jim Grosbach f2e74df12e Missing piece of the ARM frame index post-scavenging conditionalization
llvm-svn: 84798
2009-10-21 23:40:56 +00:00
Jim Grosbach 05536f50dc Conditionalize ARM/T2 frame index post-scavenging while working out fixes
for a few bugs.

llvm-svn: 84791
2009-10-21 22:59:24 +00:00
Bob Wilson 854530a7dd Most of the NEON shuffle instructions do not support 64-bit element types.
llvm-svn: 84785
2009-10-21 21:36:27 +00:00
Jim Grosbach a93ca3c637 Improve handling of immediates by splitting 32-bit immediates into two 16-bit
immediate operands when they will fit into the using instruction.

llvm-svn: 84778
2009-10-21 20:44:34 +00:00
Bob Wilson 0db964a3a0 Fix NEON VST2LN instruction encoding.
Patch by Johnny Chen.

llvm-svn: 84767
2009-10-21 17:54:01 +00:00
Bob Wilson 87671da29a Revert 84732. It was the wrong fix.
llvm-svn: 84766
2009-10-21 17:52:34 +00:00
Evan Cheng 786b15fe12 Match more patterns to movt.
llvm-svn: 84751
2009-10-21 08:15:52 +00:00
Chris Lattner 175d04c90f tidy
llvm-svn: 84738
2009-10-21 04:10:24 +00:00
Bob Wilson 5b5cb92816 Fix some more NEON instruction encoding problems.
Thanks to Johnny Chen for discovering the problem.

llvm-svn: 84732
2009-10-21 02:27:20 +00:00
Bob Wilson bd3650cc84 Leave some NEON instruction encoding bits unspecified instead of setting
a default value of zero.  This is important for decoding the instructions.
Patch by Johnny Chen, with some changes from me, too.

llvm-svn: 84730
2009-10-21 02:15:46 +00:00
Daniel Dunbar a470eac6a1 Fix -Asserts warning.
llvm-svn: 84687
2009-10-20 22:10:05 +00:00
Jim Grosbach cccf5084a3 Disable by default while debugging
llvm-svn: 84669
2009-10-20 20:31:31 +00:00
Jim Grosbach f3a2b6499e add cmd line opt to disable frame index reuse for ARM and T2. debug aid.
llvm-svn: 84664
2009-10-20 20:19:50 +00:00
Benjamin Kramer 3301207a15 Random #include pruning.
llvm-svn: 84632
2009-10-20 11:44:38 +00:00
Chris Lattner 9351e4f4b2 implement some more easy hooks.
llvm-svn: 84614
2009-10-20 06:22:33 +00:00
Chris Lattner 60d5131653 Implement some hooks, make printOperand abort if unknown modifiers are
present.

llvm-svn: 84613
2009-10-20 06:15:28 +00:00
Chris Lattner 227767b4e5 t2MOVi32imm is currently always lowered by the Thumb2ITBlockPass.
llvm-svn: 84611
2009-10-20 05:58:02 +00:00
Daniel Dunbar f0b3d15cfe Wire up the ARM MCInst printer, for llvm-mc.
llvm-svn: 84600
2009-10-20 05:15:36 +00:00
Jim Grosbach 34f040a575 Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*
functions are not needed.

llvm-svn: 84587
2009-10-20 01:32:47 +00:00
Jim Grosbach 84f6235b6f Enable post-pass frame index register scavenging for ARM and Thumb2
llvm-svn: 84585
2009-10-20 01:26:58 +00:00
Chris Lattner 484d2e9491 lower ARM::MOVi32imm properly.
llvm-svn: 84583
2009-10-20 01:11:37 +00:00
Chris Lattner 43c5589a7e add support for external symbols. The mc instprinter can now handle
reasonable code like Codegen/ARM/2009-02-27-SpillerBug.ll, producing 
identical output except for superior formatting of constant pool entries.

llvm-svn: 84582
2009-10-20 00:56:16 +00:00
Chris Lattner 1b06acbd70 get fancy: support basic block operands. Yay for jumps.
llvm-svn: 84579
2009-10-20 00:52:47 +00:00
Chris Lattner 85ab670644 add supprort for the 'sbit' operand, MOVi apparently has one.
llvm-svn: 84577
2009-10-20 00:46:11 +00:00
Chris Lattner 19c52201bd add support for instruction predicates.
llvm-svn: 84575
2009-10-20 00:42:49 +00:00
Chris Lattner 2f69ed8f4c implement printSORegOperand, add lowering for the nasty and despicable MOVi2pieces :)
llvm-svn: 84573
2009-10-20 00:40:56 +00:00
Jim Grosbach 772b2f84eb Refs: A8-598.
Leave Inst{11-8}, which represents the starting byte index of the extracted
result in the concatenation of the operands and is left unspecified.

Patch by Johnny Chen.

llvm-svn: 84572
2009-10-20 00:38:19 +00:00
Jim Grosbach 68f495caad Add missing encoding bits to NLdSt class of instructions.
Patch by Johnny Chen.

llvm-svn: 84570
2009-10-20 00:19:08 +00:00
Chris Lattner bd531262f8 handle addmode4 modifiers, fix a fixme in printRegisterList
by ignoring all implicit regs when lowering.

llvm-svn: 84566
2009-10-19 23:31:43 +00:00
Jim Grosbach f5f263f1b4 Enable allocation of R3 in Thumb1
llvm-svn: 84563
2009-10-19 22:57:03 +00:00
Chris Lattner d91c11091d use EmitLabel instead of text emission
llvm-svn: 84562
2009-10-19 22:51:16 +00:00
Chris Lattner 86dfd73c38 add a twine version of MCContext::GetOrCreateSymbol.
llvm-svn: 84561
2009-10-19 22:49:00 +00:00
Chris Lattner 186c6b0834 lower the ARM::CONSTPOOL_ENTRY pseudo op, giving us constant pool entries
like:

@ BB#1:
	.align	2
LCPI1_0:
	.long	L_.str-(LPC0+8)

Note that proper indentation of the label :)

llvm-svn: 84558
2009-10-19 22:33:05 +00:00
Jim Grosbach 5a5a3bc5d4 Adjust the scavenge register spilling to allow the target to choose an
appropriate restore location for the spill as well as perform the actual
save and restore.

The Thumb1 target uses this to make sure R12 is not clobbered while a spilled
scavenger register is live there.

llvm-svn: 84554
2009-10-19 22:27:30 +00:00
Chris Lattner add5749ac8 add MCInstLower support for lowering ARM::PICADD, a pseudo op for pic stuffola.
llvm-svn: 84553
2009-10-19 22:23:04 +00:00
Chris Lattner ef2979b1da add register list and hacked up addrmode #4 support, we now get this:
_main:
	stmsp! sp!, {r7, lr}
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldmsp! sp!, {r7, pc}

Note the unhappy ldm/stm because of modifiers being ignored.

llvm-svn: 84546
2009-10-19 22:09:23 +00:00
Chris Lattner 7ddfdc4133 add addrmode2 support, getting us up to:
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, [sp]
	ldr r0, LCPI1_0
	bl _printf
	ldr r0, [sp]
	mov sp, r7
	ldm , 

llvm-svn: 84543
2009-10-19 21:57:05 +00:00
Chris Lattner 889a6217fa add jump tables, constant pools and some trivial global
lowering stuff.  We can now compile hello world to:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 
	ldr r0, 
	bl _printf
	ldr r0, 
	mov sp, r7
	ldm , 

Almost looks like arm code :)

llvm-svn: 84542
2009-10-19 21:53:00 +00:00
Chris Lattner 8bd9b9d3fa reduce #includes
llvm-svn: 84536
2009-10-19 21:23:15 +00:00
Chris Lattner 89d47205b5 add printing support for SOImm operands, getting us to:
_main:
	stm , 
	mov r7, sp
	sub sp, sp, #4
	mov r0, #0
	str r0, 

llvm-svn: 84535
2009-10-19 21:21:39 +00:00
Chris Lattner 93e3ef6536 wire up some basic printOperand goodness, giving us stuff like this before
we abort:

_main:
	stm , 
	mov r7, sp
	sub sp, sp, 
	mov r0, 
	str r0, 

llvm-svn: 84532
2009-10-19 20:59:55 +00:00
Chris Lattner 78393d79a0 add the files that go with the previous rev
llvm-svn: 84531
2009-10-19 20:21:05 +00:00
Chris Lattner 71eb077c15 wire up skeletal support for having llc print instructions
through mcinst lowering -> mcinstprinter, when llc is passed
the -enable-arm-mcinst-printer flag.  Currently this
is very "aborty".

llvm-svn: 84530
2009-10-19 20:20:46 +00:00
Chris Lattner 296544e15f wire up ARM's printMCInst method. Now llvm-mc should be able to produce
"something" when printing MCInsts, it will just be missing all the 
operand info.

llvm-svn: 84528
2009-10-19 19:59:05 +00:00
Chris Lattner a290778859 stub out a minimal ARMInstPrinter.
llvm-svn: 84527
2009-10-19 19:56:26 +00:00
Chris Lattner 8d2e3a28d6 simplify code, reducing string thrashing.
llvm-svn: 84521
2009-10-19 18:49:14 +00:00
Chris Lattner 3334deb19b switch hidden gv stubs to use MachineModuleInfoMachO instead of a custom map.
llvm-svn: 84520
2009-10-19 18:44:38 +00:00
Chris Lattner 6462adcd20 use MachineModuleInfoMachO for non-lazy gv stubs instead of a private map.
llvm-svn: 84519
2009-10-19 18:38:33 +00:00
Chris Lattner 24fcb826bd remove dead map
llvm-svn: 84513
2009-10-19 18:11:25 +00:00
Chris Lattner 84a493ca21 don't bother trying to avoid emitting redundant constant pool alignment directives.
llvm-svn: 84512
2009-10-19 18:08:02 +00:00
Chris Lattner e6da1826e8 emit .subsections_via_symbols through MCStreamer instead of textually.
llvm-svn: 84509
2009-10-19 18:03:08 +00:00
Chris Lattner ee9399acaa cleanup doFinalization -> EmitEndOfAsmFile.
llvm-svn: 84508
2009-10-19 17:59:19 +00:00
Evan Cheng 0e9d9ca855 -Revert parts of 84326 and 84411. Distinquishing between fixed and non-fixed
stack slots and giving them different PseudoSourceValue's did not fix the
problem of post-alloc scheduling miscompiling llvm itself.
- Apply Dan's conservative workaround by assuming any non fixed stack slots can
alias other memory locations. This means a load from spill slot #1 cannot 
move above a store of spill slot #2. 
- Enable post-alloc scheduling for x86 at optimization leverl Default and above.

llvm-svn: 84424
2009-10-18 18:16:27 +00:00
Evan Cheng 4729191bb2 Distinquish stack slots from other stack objects. They (and fixed objects) get FixedStack PseudoSourceValues.
llvm-svn: 84326
2009-10-17 09:20:14 +00:00
Evan Cheng 8759585aba Revert 84315 for now. Re-thinking the patch.
llvm-svn: 84321
2009-10-17 07:53:04 +00:00
Evan Cheng 0818d87ed1 Rename getFixedStack to getStackObject. The stack objects represented are not
necessarily fixed. Only those will negative frame indices are "fixed."

llvm-svn: 84315
2009-10-17 06:22:26 +00:00
Evan Cheng 007ceb4603 Change createPostRAScheduler so it can be turned off at llc -O1.
llvm-svn: 84273
2009-10-16 21:06:15 +00:00
Evan Cheng 343d17d762 I am no spelling bee.
llvm-svn: 84250
2009-10-16 06:18:09 +00:00
Evan Cheng 03da4dba59 Enable post-alloc scheduling for all ARM variants except for Thumb1.
llvm-svn: 84249
2009-10-16 06:11:08 +00:00
Evan Cheng 8cd7c92613 Add comment.
llvm-svn: 84246
2009-10-16 05:33:58 +00:00
Bob Wilson 01404ecec7 Fix more NEON instruction encodings.
Patch by Johnny Chen.

llvm-svn: 84243
2009-10-16 03:58:44 +00:00
Bob Wilson 419160bd79 Revert svn r80498 and replace it with a different solution. The only problem
I can see with the original code was that I forgot that this runs after
type legalization and hence the result type will always be i32. (Custom
legalization of EXTRACT_VECTOR_ELT is only enabled for vector types with
8- and 16-bit elements.)

Regarding the FIXME comment: any information about sign and zero-extension
should be captured by separate extension operations.  The DAG combiner should
handle those to produce either VGETLANEu or VGETLANEs, and that seems to be
working now.  If there are cases that we're missing, let me know.

llvm-svn: 84218
2009-10-15 23:12:05 +00:00
Sandeep Patel 3f23601b00 Branches must be the last instruction in a Thumb2 IT block. Approved by Evan Cheng.
llvm-svn: 84212
2009-10-15 22:25:32 +00:00
Bob Wilson 4138b11c93 Fix encoding bits for N3VLInt3_QHS multiclass with 8-bit elements.
Patch by Johnny Chen.

llvm-svn: 84206
2009-10-15 21:57:47 +00:00
Kevin Enderby 644de27659 Fix ARM memory operand parsing of post indexing with just a base register, that
is just "[Rn]" and no tailing comma with an offset, etc.

llvm-svn: 84205
2009-10-15 21:42:45 +00:00
Bob Wilson 2f9be50774 Fix a potential performance problem in placing ARM constant pools.
In the case where there are no good places to put constants and we fall back
upon inserting unconditional branches to make new blocks, allow all constant
pool references in range of those blocks to put constants there, even if that
means resetting the "high water marks" for those references.  This will still
terminate because you can't keep splitting blocks forever, and in the bad
cases where we have to split blocks, it is important to avoid splitting more
than necessary.

llvm-svn: 84202
2009-10-15 20:49:47 +00:00
Kevin Enderby 146dcf2ab5 More bits of the ARM target assembler for llvm-mc, code added to parse labels
as expressions, code for parsing a few arm specific directives (still needs
the MCStreamer calls for these).  Some clean up of the operand parsing code
and adding some comments.

llvm-svn: 84201
2009-10-15 20:48:48 +00:00
Bob Wilson 68ead6c7a8 Be smarter about reusing constant pool entries.
llvm-svn: 84173
2009-10-15 05:52:29 +00:00
Bob Wilson b4f2a85fe4 Fix another problem with ARM constant pools. Radar 7303551.
When ARMConstantIslandPass cannot find any good locations (i.e., "water") to
place constants, it falls back to inserting unconditional branches to make a
place to put them.  My recent change exposed a problem in this area.  We may
sometimes append to the same block more than one unconditional branch.  The
symptoms of this are that the generated assembly has a branch to an undefined
label and running llc with -debug will cause a seg fault.

This happens more easily since my change to prevent CPEs from moving from
lower to higher addresses as the algorithm iterates, but it could have
happened before.  The end of the block may be in range for various constant
pool references, but the insertion point for new CPEs is not right at the end
of the block -- it is at the end of the CPEs that have already been placed
at the end of the block.  The insertion point could be out of range.  When
that happens, the fallback code will always append another unconditional
branch if the end of the block is in range.

The fix is to only append an unconditional branch if the block does not
already end with one.  I also removed a check to see if the constant pool load
instruction is at the end of the block, since that is redundant with
checking if the end of the block is in-range.

There is more to be done here, but I think this fixes the immediate problem.

llvm-svn: 84172
2009-10-15 05:10:36 +00:00
Bob Wilson cfcf6bc70d Fix instruction encoding bits for NEON VPADAL.
Patch by Johnny Chen.

llvm-svn: 84146
2009-10-14 21:43:17 +00:00
Bob Wilson ad03cf02f6 Remove unused variables to fix build warning.
llvm-svn: 84144
2009-10-14 21:40:45 +00:00
Jim Grosbach 94068707e1 Inst{11-8} for vshl should be 0b0101, not 0b1111.
Refs: A7-17 & A8-750.

Patch by Johnny Chen.

llvm-svn: 84131
2009-10-14 20:31:01 +00:00
Bob Wilson 1a791eedbf Set instruction encoding bits 4 and 7 for ARM register-register and
register-shifted-register instructions.  Patch by Johnny Chen.

llvm-svn: 84124
2009-10-14 19:00:24 +00:00
Bob Wilson c350cdf3b3 Refactor code to select NEON VST intrinsics.
llvm-svn: 84122
2009-10-14 18:32:29 +00:00
Bob Wilson 12b4799787 Refactor code to select NEON VLD intrinsics.
llvm-svn: 84117
2009-10-14 17:28:52 +00:00
Bob Wilson 93117bc499 More refactoring. NEON vst lane intrinsics can share almost all the code for
vld lane intrinsics.

llvm-svn: 84110
2009-10-14 16:46:45 +00:00
Bob Wilson 4145e3ac8d Refactor code for selecting NEON load lane intrinsics.
llvm-svn: 84109
2009-10-14 16:19:03 +00:00
Kevin Enderby 3a80daced0 Correct comment about ARM immediates using '#' not '$' and TODO for modifiers.
llvm-svn: 84055
2009-10-13 23:33:38 +00:00
Bob Wilson b62d160b3c More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics
by creating TargetConstants during instruction selection instead of during
legalization.

llvm-svn: 84042
2009-10-13 22:29:24 +00:00
Kevin Enderby f50799412c More bits of the ARM target assembler for llvm-mc to parse immediates.
Also fixed a couple of coding style things that crept in.  And added more
to the temporary hacked up ARMAsmParser::MatchInstruction() method for testing.

llvm-svn: 84040
2009-10-13 22:19:02 +00:00
Bob Wilson 1fdbe1152d NEON VLD/VST are now fully implemented. For operations that expand to
multiple instructions, the expansion is done during selection so there is
no need to do anything special during legalization.

llvm-svn: 84036
2009-10-13 21:55:24 +00:00
Bob Wilson 3b51560ae4 Revise ARM inline assembly memory operands to require the memory address to
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
2009-10-13 20:50:28 +00:00
Sandeep Patel 7460e0822f Fix method name in comment, per Bob Wilson.
llvm-svn: 84017
2009-10-13 20:25:58 +00:00
Sandeep Patel 423e42b371 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov.
llvm-svn: 84009
2009-10-13 18:59:48 +00:00
Bob Wilson 453a06e3ac Add some ARM instruction encoding bits.
Patch by Johnny Chen.

llvm-svn: 83983
2009-10-13 17:35:30 +00:00
Bob Wilson d26a26ae7e Fix regression introduced by r83894.
llvm-svn: 83982
2009-10-13 17:29:13 +00:00
Bob Wilson 0bc673de0d Fix a tab. Thanks to Johnny Chen for pointing it out.
llvm-svn: 83973
2009-10-13 15:27:23 +00:00
Kevin Enderby 11b32384f2 Fix two warnings about unused variables that are only used in assert() calls.
llvm-svn: 83917
2009-10-12 22:51:49 +00:00
Bob Wilson 5b07a903d4 Delete a comment that makes no sense to me. The statement that moving a CPE
before its reference is only supported on ARM has not been true for a while.
In fact, until recently, that was only supported for Thumb.  Besides that,
CPEs are always a multiple of 4 bytes in size, so inserting a CPE should have
no effect on Thumb alignment.

llvm-svn: 83916
2009-10-12 22:49:05 +00:00
Kevin Enderby 3f0b9b3db4 Fix a problem in the code where ARMAsmParser::ParseShift() second argument
should have been a pointer to a reference.

llvm-svn: 83915
2009-10-12 22:39:54 +00:00
Bob Wilson 3250e7769f Change CreateNewWater method to return NewMBB by reference.
llvm-svn: 83905
2009-10-12 21:39:43 +00:00
Bob Wilson cc121aa750 Last week, ARMConstantIslandPass was failing to converge for the
MultiSource/Benchmarks/MiBench/automotive-susan test.  The failure has
since been masked by an unrelated change (just randomly), so I don't have
a testcase for this now.  Radar 7291928.

The situation where this happened is that a constant pool entry (CPE) was
placed at a lower address than the load that referenced it.  There were in
fact 2 CPEs placed at adjacent addresses and referenced by 2 loads that were
close together in the code.  The distance from the loads to the CPEs was
right at the limit of what they could handle, so that only one of the CPEs
could be placed within range.  On every iteration, the first CPE was found
to be out of range, causing a new CPE to be inserted.  The second CPE had
been in range but the newly inserted entry pushed it too far away.  Thus the
second CPE was also replaced by a new entry, which in turn pushed the first
CPE out of range.  Etc.

Judging from some comments in the code, the initial implementation of this
pass did not support CPEs placed _before_ their references.  In the case
where the CPE is placed at a higher address, the key to making the algorithm
terminate is that new CPEs are only inserted at the end of a group of adjacent
CPEs.  This is implemented by removing a basic block from the "WaterList"
once it has been used, and then adding the newly inserted CPE block to the
list so that the next insertion will come after it.  This avoids the ping-pong
effect where CPEs are repeatedly moved to the beginning of a group of
adjacent CPEs.  This does not work when going backwards, however, because the
entries at the end of an adjacent group of CPEs are closer than the CPEs
earlier in the group.

To make this pass terminate, we need to maintain a property that changes can
only happen in some sort of monotonic fashion.  The fix used here is to require
that the CPE for a particular constant pool load can only move to lower
addresses.  This is a very simple change to the code and should not cause
any significant degradation in the results.

llvm-svn: 83902
2009-10-12 21:23:15 +00:00
Bob Wilson e4adae267e Another minor clean-up.
llvm-svn: 83897
2009-10-12 20:45:53 +00:00
Bob Wilson 196bf32ab0 Remove redundant parameter.
llvm-svn: 83894
2009-10-12 20:37:23 +00:00
Bob Wilson 3a7326e705 Use early exit to reduce indentation.
llvm-svn: 83874
2009-10-12 19:04:03 +00:00
Bob Wilson 3af34312d4 Change to return a value by reference.
llvm-svn: 83873
2009-10-12 19:01:12 +00:00
Bob Wilson c7a3cf4066 Add a typedef for an iterator.
llvm-svn: 83872
2009-10-12 18:52:13 +00:00