Commit Graph

48415 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes 178fb40612 - Register v16i16 as valid VR256 register class
- Add more bitcasts for v16i16
- Since 135661 and 135662 already added the splat logic,
just add one more splat test for v16i16

llvm-svn: 135663
2011-07-21 02:24:08 +00:00
Bruno Cardoso Lopes b878caa5e2 Add support for 256-bit versions of VPERMIL instruction. This is a new
instruction introduced in AVX, which can operate on 128 and 256-bit vectors.
It considers a 256-bit vector as two independent 128-bit lanes. It can permute
any 32 or 64 elements inside a lane, and restricts the second lane to
have the same permutation of the first one. With the improved splat support
introduced early today, adding codegen for this instruction enable more
efficient 256-bit code:

Instead of:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vextractf128  $1, %ymm0, %xmm1
  shufps  $1, %xmm1, %xmm1
  movss %xmm1, 28(%rsp)
  movss %xmm1, 24(%rsp)
  movss %xmm1, 20(%rsp)
  movss %xmm1, 16(%rsp)
  vextractf128  $0, %ymm0, %xmm0
  shufps  $1, %xmm0, %xmm0
  movss %xmm0, 12(%rsp)
  movss %xmm0, 8(%rsp)
  movss %xmm0, 4(%rsp)
  movss %xmm0, (%rsp)
  vmovaps (%rsp), %ymm0
We get:
  vextractf128  $0, %ymm0, %xmm0
  punpcklbw %xmm0, %xmm0
  punpckhbw %xmm0, %xmm0
  vinsertf128 $0, %xmm0, %ymm0, %ymm1
  vinsertf128 $1, %xmm0, %ymm1, %ymm0
  vpermilps $85, %ymm0, %ymm0

llvm-svn: 135662
2011-07-21 01:55:47 +00:00
Bruno Cardoso Lopes fb4920eb25 Improve splat promotion to handle AVX types: v32i8 and v16i16. Also
refactor the code and add a bunch of comments. The final shuffle
emitted by handling 256-bit types is suitable for the VPERM shuffle
instruction which is going to be introduced in a next commit (with
a testcase which cover this commit)

llvm-svn: 135661
2011-07-21 01:55:42 +00:00
Bruno Cardoso Lopes 18a8d25b62 Add aditional patterns for vextractf128 instruction
llvm-svn: 135660
2011-07-21 01:55:39 +00:00
Bruno Cardoso Lopes 2389881b69 Add aditional patterns for vinsertf128 instruction
llvm-svn: 135659
2011-07-21 01:55:36 +00:00
Bruno Cardoso Lopes 0a57b22588 Add v16i16 type to VR256 class
llvm-svn: 135658
2011-07-21 01:55:33 +00:00
Bruno Cardoso Lopes e6f8832631 Move code around. No functionality changes
llvm-svn: 135657
2011-07-21 01:55:30 +00:00
Bruno Cardoso Lopes 0bdeacf03b Tidy up code
llvm-svn: 135656
2011-07-21 01:55:27 +00:00
Andrew Trick bd243d0dfe LSR, correct fix for rdar://9786536. Silly casting bug.
llvm-svn: 135654
2011-07-21 01:45:54 +00:00
Andrew Trick 858e9f083d LSR must sometimes sign-extend before generating double constants.
rdar://9786536

llvm-svn: 135650
2011-07-21 01:05:01 +00:00
Bill Wendling 28b6e12d9d Mark instructions which are part of the frame setup with the MachineInstr::FrameSetup flag.
llvm-svn: 135645
2011-07-21 00:44:56 +00:00
Andrew Trick 8acb434402 LSR crashes on an empty IVUsers list.
rdar://9786536

llvm-svn: 135644
2011-07-21 00:40:04 +00:00
Evan Cheng c3035d6657 X86 is the only target that uses coff format. This should fixes test failures running on Windows, Cygwin, or MingW hosts.
llvm-svn: 135639
2011-07-20 23:53:54 +00:00
Evan Cheng a20cde31e7 Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.
llvm-svn: 135636
2011-07-20 23:34:39 +00:00
Bill Wendling ed93564c7a Remove unused function.
llvm-svn: 135635
2011-07-20 23:07:42 +00:00
Bill Wendling 01bd7d9dc0 Remove the now defunct getCompactUnwindEncoding method from the frame lowering code.
llvm-svn: 135634
2011-07-20 23:04:09 +00:00
Devang Patel ddfe66e948 Refactor.
llvm-svn: 135633
2011-07-20 23:00:27 +00:00
Devang Patel 8fb9fd6769 There are two ways to map a variable to its lexical scope. Lexical scope information is embedded in MDNode describing the variable. It is also available as a part of DebugLoc attached with DBG_VALUE instruction. DebugLoc attached with an instruction is less reliable in optimized code so use information embedded in the MDNode.
llvm-svn: 135629
2011-07-20 22:18:50 +00:00
Eli Friedman 911e12f505 Clean up includes of llvm/Analysis/ConstantFolding.h so it's included where it's used and not included where it isn't.
llvm-svn: 135628
2011-07-20 21:57:23 +00:00
Devang Patel bcd50a10d5 While emitting constant value, look through derived type and use underlying basic type to determine size and signness of the constant value.
llvm-svn: 135627
2011-07-20 21:57:04 +00:00
Jim Grosbach a288b1c10a ARM PKH shift ammount operand printing tweaks.
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.

llvm-svn: 135626
2011-07-20 21:40:26 +00:00
Eli Friedman 0cdc148ab8 Bring LICM into compliance with the new "Memory Model for Concurrent Operations" in LangRef.
llvm-svn: 135625
2011-07-20 21:37:47 +00:00
Jim Grosbach 94df3be987 Tidy up a bit.
Move common definitions for ARM and Thumb2 into ARMInstrFormats.td and rename
them to be a bit more descriptive that they're for the PKH instructions.

llvm-svn: 135617
2011-07-20 20:49:03 +00:00
Jim Grosbach a98f80095b ARM: Tidy up representation of PKH instruction.
The shift type is implied by the instruction (PKHBT vs. PKHTB) and so shouldn't
be also encoded as part of the shift value immediate. Otherwise we're able to
represent invalid instructions, plus it needlessly complicates the
representation. Preparatory work for asm parsing of these instructions.

llvm-svn: 135616
2011-07-20 20:32:09 +00:00
Benjamin Kramer e6f7f914db Fix cmake again :)
llvm-svn: 135613
2011-07-20 20:00:06 +00:00
Evan Cheng bbf3b0de8b Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.
There is still a bit more refactoring left to do in Targets. But we are now very
close to fixing all the layering issues in MC.

llvm-svn: 135611
2011-07-20 19:50:42 +00:00
Eli Friedman ae60b6b008 Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.
llvm-svn: 135607
2011-07-20 19:36:11 +00:00
Jim Grosbach 8d11490771 ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.

llvm-svn: 135596
2011-07-20 18:20:31 +00:00
Eli Friedman 6ed783228d PR10421: Fix a straightforward bug in the widening logic for CONCAT_VECTORS.
llvm-svn: 135595
2011-07-20 18:14:33 +00:00
Benjamin Kramer acb9ed4077 Initialize the EHFrameSection pointer to zero.
This should fix the spurious buildbot errors.

llvm-svn: 135594
2011-07-20 18:13:23 +00:00
Jay Foad 50bfbab033 Fix a GCC warning.
llvm-svn: 135581
2011-07-20 08:15:21 +00:00
Evan Cheng efd9b4240f - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.
- Introduce JITDefault code model. This tells targets to set different default
  code model for JIT. This eliminates the ugly hack in TargetMachine where
  code model is changed after construction.

llvm-svn: 135580
2011-07-20 07:51:56 +00:00
Evan Cheng 345b6b45c1 Include MCRegisterInfo to eliminate a compilation warning.
llvm-svn: 135575
2011-07-20 06:54:19 +00:00
Francois Pichet e3063f022b Fix the CMake build.
llvm-svn: 135573
2011-07-20 06:35:24 +00:00
Evan Cheng 76792992d6 Add MCObjectFileInfo and sink the MCSections initialization code from
TargetLoweringObjectFileImpl down to MCObjectFileInfo.

TargetAsmInfo is done to one last method. It's *almost* gone!

llvm-svn: 135569
2011-07-20 05:58:47 +00:00
Andrew Trick 638b355a16 indvars: Added getInsertPointForUses to find a valid place to truncate the IV.
llvm-svn: 135568
2011-07-20 05:32:06 +00:00
Andrew Trick 2210448520 indvars -disable-iv-rewrite: Add NarrowIVDefUse to cache def-use
info. Holding Use* pointers is bad form even though it happened to
work in this case.

llvm-svn: 135566
2011-07-20 04:39:24 +00:00
NAKAMURA Takumi b66d255595 X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, to appease test/CodeGen/X86 on cygwin.
llvm-svn: 135564
2011-07-20 04:02:20 +00:00
Eric Christopher 954bdafb50 Extra semi-colon.
llvm-svn: 135561
2011-07-20 02:44:39 +00:00
Andrew Trick c5dd3e976a indvars -disable-iv-rewrite fix: derived GEP IVs
llvm-svn: 135558
2011-07-20 02:08:58 +00:00
Benjamin Kramer cc38ef6d84 Don't leak CodeGenInfos.
llvm-svn: 135555
2011-07-20 01:27:58 +00:00
Akira Hatanaka 170581488f Change name of class.
llvm-svn: 135550
2011-07-20 00:53:09 +00:00
Akira Hatanaka 969edcdf74 Define classes for definitions of atomic instructions.
llvm-svn: 135546
2011-07-20 00:23:01 +00:00
Akira Hatanaka a4c09bce9b Lower memory barriers to sync instructions.
llvm-svn: 135537
2011-07-19 23:30:50 +00:00
Evan Cheng ccf243d56b Fix an obvious typo that's preventing x86 (32-bit) from using .literal16.
llvm-svn: 135535
2011-07-19 23:14:32 +00:00
Eli Friedman 55d6ccbb79 PR10386: Don't try to split an edge from an indirectbr.
llvm-svn: 135534
2011-07-19 22:59:41 +00:00
Jim Grosbach d25c2cdad7 Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.

llvm-svn: 135532
2011-07-19 22:45:10 +00:00
Devang Patel a59b24b090 Distinguish between two copies of one inlined variable.
llvm-svn: 135528
2011-07-19 22:31:15 +00:00
Jim Grosbach 97094d8f06 ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.

llvm-svn: 135527
2011-07-19 21:59:29 +00:00
Owen Anderson c78e03c39a Enhance the FixedLengthDecoder to be able to generate plausible-looking decoders for ARM.
llvm-svn: 135524
2011-07-19 21:06:00 +00:00