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3 Commits

Author SHA1 Message Date
Matt Arsenault 663ab8c119 AMDGPU: Use brev for materializing SGPR constants 
This is already done with VGPR immediates and saves 4 bytes.

llvm-svn: 285765
 2016-11-01 23:14:20 +00:00
Matt Arsenault 2b957b5a6f AMDGPU: Make i64 loads/stores promote to v2i32 
Now that unaligned access expansion should not attempt
to produce i64 accesses, we can remove the hack in
PreprocessISelDAG where this is done.

This allows splitting i64 private accesses while
allowing the new add nodes indexing the vector components
can be folded with the base pointer arithmetic.

llvm-svn: 268293
 2016-05-02 20:07:26 +00:00
Matt Arsenault 9a19c240c0 AMDGPU: Materialize sign bits with bfrev 
If a constant is the same as the reverse of an inline immediate,
this is 4 bytes smaller than having to embed a 32-bit literal.

llvm-svn: 263201
 2016-03-11 07:42:49 +00:00