maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
174,844 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

107 Commits

Author SHA1 Message Date
Matt Arsenault d504a74e3c Use range for 
llvm-svn: 208922
 2014-05-15 21:44:05 +00:00
Jay Foad a0653a3e6c Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
 2014-05-14 21:14:37 +00:00
Matt Arsenault 62b1737081 R600: Add mul24 intrinsics 
llvm-svn: 208604
 2014-05-12 17:49:57 +00:00
Matt Arsenault 46013d903f Fix return before else 
llvm-svn: 208510
 2014-05-11 21:24:41 +00:00
Tom Stellard a2acad785a R600: Expand i64 SELECT_CC 
llvm-svn: 208430
 2014-05-09 16:42:19 +00:00
Tom Stellard afa8b532b1 R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 
llvm-svn: 208429
 2014-05-09 16:42:16 +00:00
Matt Arsenault e8a076a253 R600: Promote f64 vector load/stores to i64 for consistency 
llvm-svn: 208344
 2014-05-08 18:01:56 +00:00
Tom Stellard 45b3dcd35b R600: Expand i64 ISD:SUB 
llvm-svn: 208005
 2014-05-05 21:47:15 +00:00
Tom Stellard 3dbf1f8df0 R600: Expand vector sin and cos. 
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 207845
 2014-05-02 15:41:47 +00:00
Tom Stellard 605e116e8e R600: Expand TruncStore i64 -> {i16,i8} 
llvm-svn: 207844
 2014-05-02 15:41:46 +00:00
Tom Stellard 676f571999 R600: optimize the UDIVREM 64 algorithm 
This is a squash of several optimization commits:
 - calculate DIV_Lo and DIV_Hi separately
 - use BFE_U32 if we are operating on 32bit values
 - use precomputed constants instead of shifting in UDVIREM
 - skip the first 32 iterations of udivrem

v2: Check whether BFE is supported before using it

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 207589
 2014-04-29 23:12:46 +00:00
Tom Stellard bcd318fc76 R600: Implement iterative algorithm for udivrem 
Initial implementation, rather slow

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 207588
 2014-04-29 23:12:45 +00:00
Tom Stellard 5f3378879f R600: Change UDIV/UREM to UDIVREM when legalizing types 
When legalizing ops, with UDIV/UREM set to expand, they automatically
expand to UDIVREM (if legal or custom).
We need to do this manually for legalize types.

v2:
  SI should be set to Expand because the type is legal, and it is
    automatically lowered to UDIVREM if UDIVREM is Legal/Custom
  R600 should set to UDIV/UREM to Custom because it needs to lower them
    during type legalization

Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 207587
 2014-04-29 23:12:43 +00:00
Tom Stellard df780303ef R600: remove unused variable 
Patch by: Jan Vesely

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 207586
 2014-04-29 23:12:38 +00:00
Craig Topper 8c0b4d0791 Convert more SelectionDAG functions to use ArrayRef. 
llvm-svn: 207397
 2014-04-28 05:57:50 +00:00
Craig Topper 64941d9786 Convert SelectionDAG::getMergeValues to use ArrayRef. 
llvm-svn: 207374
 2014-04-27 19:20:57 +00:00
Craig Topper 48d114bed1 Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>. 
llvm-svn: 207327
 2014-04-26 18:35:24 +00:00
Matt Arsenault de1c3410c3 R600: Fix function name printing in LowerCall 
v2: Check both ExternalSymbol and GlobalAddress

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

llvm-svn: 207282
 2014-04-25 22:22:01 +00:00
Craig Topper 062a2baef0 [C++] Use 'nullptr'. Target edition. 
llvm-svn: 207197
 2014-04-25 05:30:21 +00:00
Matt Arsenault 16353871c3 R600: Emit error instead of unreachable on function call 
llvm-svn: 206904
 2014-04-22 16:42:00 +00:00
Matt Arsenault a3c8cde77b R600: Change how vector truncating stores are packed. 
Don't introduce new operations on an illegal sub 32-bit type.
Do the operations on a 32-bit value, and then use a truncating store.

llvm-svn: 206864
 2014-04-22 04:11:14 +00:00
Matt Arsenault 5dbd5db518 R600: Make sign_extend_inreg legal. 
Don't know why I didn't just do this in the first place.

llvm-svn: 206862
 2014-04-22 03:49:30 +00:00
Tom Stellard aeeea8a864 R600: Add comment clariying use of sext for result of MUL_U24 
llvm-svn: 206501
 2014-04-17 21:00:13 +00:00
Matt Arsenault 4e46665a80 R600: Expand sign extension of vectors. 
Setting vector types to expand will result in scalarization on pre SI hw,
as those gpus don't have vector shifts either.
Expand also i32 vectors, this helps llvm make the correct decision
about scalarizing the vector ops.

v2: move setOperation() calls to R600ISelLowering.cpp.
    cleanup the SI code to make it obvious that this patch does is nop for SI

Patch by: Jan Vesely <jan.vesely@rutgers.edu>

llvm-svn: 206348
 2014-04-16 01:41:30 +00:00
Matt Arsenault 470acd81a8 R600/SI: Fix loads of i1 
llvm-svn: 206330
 2014-04-15 22:28:39 +00:00
Nick Lewycky aad475b324 Break PseudoSourceValue out of the Value hierarchy. It is now the root of its own tree containing FixedStackPseudoSourceValue (which you can use isa/dyn_cast on) and MipsCallEntry (which you can't). Anything that needs to use either a PseudoSourceValue* and Value* is strongly encouraged to use a MachinePointerInfo instead. 
llvm-svn: 206255
 2014-04-15 07:22:52 +00:00
Matt Arsenault 9ec3cf2c8a Move ExtractVectorElements to SelectionDAG. 
This seems generally useful, and makes sense to
go along with SplitVector.

llvm-svn: 206041
 2014-04-11 17:47:30 +00:00
Tom Stellard 50122a5890 R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

llvm-svn: 205731
 2014-04-07 19:45:41 +00:00
Matt Arsenault 7939acd7fa Use .data() instead of &x[0] 
llvm-svn: 205722
 2014-04-07 16:44:24 +00:00
Matt Arsenault 378bf9c68b R600: Compute masked bits for min and max 
llvm-svn: 205242
 2014-03-31 19:35:33 +00:00
Matt Arsenault 4c53717787 R600: Add BFE, BFI, and BFM intrinsics to help with writing tests. 
llvm-svn: 205236
 2014-03-31 18:21:18 +00:00
Matt Arsenault b34583661b R600: Add target nodes for BFM and BFI 
llvm-svn: 205235
 2014-03-31 18:21:13 +00:00
Matt Arsenault b517c8128e R600: Implement isZExtFree. 
This allows 64-bit operations that are truncated to be reduced
to 32-bit ones.

llvm-svn: 204946
 2014-03-27 17:23:31 +00:00
Matt Arsenault d125d74a73 R600/SI: Fix unreachable with a sext_in_reg to an illegal type. 
llvm-svn: 204945
 2014-03-27 17:23:24 +00:00
Matt Arsenault 90b733a3cf R600: Add a testcase for sext_in_reg I missed. 
This sext_inreg i32 in i64 case was already handled, but not enabled.

llvm-svn: 204840
 2014-03-26 18:31:06 +00:00
Matt Arsenault 0c274feedf R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp 
Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

llvm-svn: 204743
 2014-03-25 18:18:27 +00:00
Matt Arsenault a7f1e0c44f R600: Implement isNarrowingProfitable. 
llvm-svn: 204658
 2014-03-24 19:43:31 +00:00
Matt Arsenault fae02989b7 R600: Match sign_extend_inreg to BFE instructions 
llvm-svn: 204072
 2014-03-17 18:58:11 +00:00
Matt Arsenault ea330fbe49 R600: Remove unnecessary attempt to zext a pointer. 
Private pointers are now always 32-bits.

llvm-svn: 203989
 2014-03-15 00:08:26 +00:00
Matt Arsenault 74891cdefe R600: Code cleanup. 
Use sign_extend_inreg and getZeroExtendInReg instead of
using the bit operations they expand into.

llvm-svn: 203988
 2014-03-15 00:08:22 +00:00
Matt Arsenault e389dd5d68 R600: Fix trunc store from i64 to i1 
llvm-svn: 203695
 2014-03-12 18:45:52 +00:00
Matt Arsenault 0211714ecb R600: Calculate store mask instead of using switch. 
llvm-svn: 203527
 2014-03-11 01:38:53 +00:00
Matt Arsenault 9504d2f269 Use .data() instead of &x[0] 
llvm-svn: 203516
 2014-03-11 00:01:31 +00:00
Matt Arsenault f9a995d68c R600: Fix extloads from i8 / i16 to i64. 
This appears to only be working for global loads. Private
and local break for other reasons.

llvm-svn: 203135
 2014-03-06 17:34:12 +00:00
Matt Arsenault 9fe669c522 R600/SI: Expand selects on vectors. 
llvm-svn: 203134
 2014-03-06 17:34:03 +00:00
Matt Arsenault ca6dcfcf59 Fix typo 
llvm-svn: 203013
 2014-03-05 21:47:22 +00:00
Matt Arsenault 41e2f2bacd R600/SI - Add new CI arithmetic instructions. 
Does not yet include larger part required
to match v_mad_i64_i32 / v_mad_u64_u32.

llvm-svn: 202077
 2014-02-24 21:01:28 +00:00
Matt Arsenault 21a3faaf25 Fix DOT4 missing from getTargetOpcodeName 
llvm-svn: 202075
 2014-02-24 21:01:21 +00:00
Tom Stellard 967bf5813f R600/SI: Expand all v8[if]32 operations 
llvm-svn: 201371
 2014-02-13 23:34:15 +00:00
Benjamin Kramer 53f9df4c93 R600: Always implement both versions of isTruncateFree and add a sanity check. 
llvm-svn: 201222
 2014-02-12 10:17:54 +00:00