Commit Graph

39 Commits

Author SHA1 Message Date
Bob Wilson 651eaa02b8 Remove the rest of the *_sfp Neon instruction patterns.
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730
2010-12-13 23:02:37 +00:00
Bill Wendling dc913e64d7 Merge DEBUG statements.
llvm-svn: 121660
2010-12-13 01:03:49 +00:00
Chris Lattner 77d369c8eb eliminate the Records global variable, patch by Garrison Venn!
llvm-svn: 121659
2010-12-13 00:23:57 +00:00
Jim Grosbach f878e62a0d Remove reference to the CMPz instruction patterns for ARM.
llvm-svn: 121180
2010-12-07 20:44:33 +00:00
Bill Wendling 4e7eb12f6f I did it wrong. Don't disregard these encodings here.
llvm-svn: 120786
2010-12-03 02:25:59 +00:00
Bill Wendling e38f1149fa Ignore decode table conflicts in the tMOVgpr2tgpr, tMOVgpr2gpr, and tMOVtgpr2gpr
instructions. They are handled as special moves, but encoded as a normal move.

llvm-svn: 120779
2010-12-03 01:55:30 +00:00
Jim Grosbach 8b16618685 The VLDMQ/VSTMQ instructions are reprented as true Pseudo-insts now (i.e.,
no extra encoding information), so we no longer need to special case them
here.

llvm-svn: 120444
2010-11-30 19:08:32 +00:00
Jim Grosbach f01da1a7df Tidy up.
llvm-svn: 120443
2010-11-30 19:00:13 +00:00
Jim Grosbach 89a4795b52 Delete a few no longer needed references to pseudos.
llvm-svn: 120441
2010-11-30 18:56:13 +00:00
Jim Grosbach 7ec3d34553 Pseudo-ize Thumb2 jump tables with explicit MC lowering to the raw
instructions. This simplifies instruction printing and disassembly.

llvm-svn: 120333
2010-11-29 22:37:40 +00:00
Jim Grosbach 81af4f9eb1 Rename t2 TBB and TBH instructions to reference that they encode the jump table
data. Next up, pseudo-izing them.

llvm-svn: 120320
2010-11-29 21:28:32 +00:00
Michael J. Spencer 447762da85 Merge System into Support.
llvm-svn: 120298
2010-11-29 18:16:10 +00:00
Bill Wendling a68e3a5397 Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>

llvm-svn: 119310
2010-11-16 01:16:36 +00:00
Chris Lattner d8adec70f3 factor the operand list (and related fields/operations) out of
CodeGenInstruction into its own helper class.  No functionality change.

llvm-svn: 117893
2010-11-01 04:03:32 +00:00
Jim Grosbach b75d0ca38e A few 80 column cleanups
llvm-svn: 116069
2010-10-08 18:13:57 +00:00
Jim Grosbach 33c1eb16e8 Move checking for t2MOVCCi16 to the right place.
llvm-svn: 115994
2010-10-07 22:14:01 +00:00
Nick Lewycky 1e00173d20 Fix typo in comment.
llvm-svn: 115986
2010-10-07 21:55:16 +00:00
Jim Grosbach 5b255c2dd6 Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode.
llvm-svn: 115890
2010-10-07 00:53:56 +00:00
Jim Grosbach 742adc328a Allow use of the 16-bit literal move instruction in CMOVs for ARM mode.
llvm-svn: 115884
2010-10-07 00:42:42 +00:00
Jim Grosbach b270f28c1a Now that VDUPfqf and VDUPfdfare properly pseudos, nuke the special handling.
llvm-svn: 115841
2010-10-06 21:17:07 +00:00
Bob Wilson aaff8f539a Fix a comment typo.
llvm-svn: 112302
2010-08-27 21:56:59 +00:00
Bob Wilson 9664984be8 Add a separate ARM instruction format for Saturate instructions.
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
2010-08-11 00:01:18 +00:00
Dale Johannesen e2289285ae Changes to ARM tail calls, mostly cosmetic.
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
2010-07-08 01:18:23 +00:00
Dale Johannesen a06c2f79fc An attempt to fix the problem Anton reported with
ARM tail calls.  Don't know if it works, but it
doesn't break Darwin.

llvm-svn: 106309
2010-06-18 20:44:28 +00:00
Dale Johannesen 44f9dfc9cf Next round of tail call changes. Register used in a tail
call must not be callee-saved; following x86, add a new
regclass to represent this.  Also fixes a couple of bugs.
Still disabled by default; Thumb doesn't work yet.

llvm-svn: 106053
2010-06-15 22:08:33 +00:00
Dale Johannesen d679ff7330 Early implementation of tail call for ARM.
A temporary flag -arm-tail-calls defaults to off,
so there is no functional change by default.
Intrepid users may try this; simple cases work
but there are bugs.

llvm-svn: 105413
2010-06-03 21:09:53 +00:00
Johnny Chen d7209d2d56 When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.

llvm-svn: 101929
2010-04-20 18:45:24 +00:00
Johnny Chen 4e8bd58001 If all the bit positions are not specified; do not decode the instructions.
We are bound to fail!  For proper disassembly, the well-known encoding bits
of the instruction must be fully specified.

This also removes pseudo instructions from considerations of disassembly,
which is a better design and less fragile than the name matchings.

llvm-svn: 100899
2010-04-09 21:01:02 +00:00
Bob Wilson 0106063556 Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets
such that the non-VFP versions have no implicit defs of VFP registers.
If any callee-saved VFP registers are marked as having been defined, the
prologue/epilogue code will try to save and restore them.
Radar 7770432.

llvm-svn: 100892
2010-04-09 20:41:18 +00:00
Johnny Chen 298a122fb4 ARM decoder emitter should print out useful information unconditionally when it
encounters decoding conflicts, instead of wrapping it inside the DEBUG() macro. 

llvm-svn: 100886
2010-04-09 19:31:33 +00:00
Johnny Chen 75f82345c4 Now that Evan Cheng has fixed the coalescer bug (r100804), the workaround code
to avoid memcpy() call is no longer necessary.

llvm-svn: 100811
2010-04-08 21:23:54 +00:00
Benjamin Kramer 53dd088b58 Various MSVC warning fixes about truncated 64 bit shifts and const pointers passed to free.
llvm-svn: 100767
2010-04-08 15:25:57 +00:00
Eric Christopher 978d33a937 Fix typo and correct comment somewhat.
llvm-svn: 100691
2010-04-07 20:58:16 +00:00
Johnny Chen 4e2f8722c4 Re-enable ARM/Thumb disassembler and add a workaround for a memcpy() call in
ARMDecoderEmitter.cpp, with FIXME comment.

llvm-svn: 100690
2010-04-07 20:53:12 +00:00
Chandler Carruth 77074b1378 Fix a warning in GCC about a pointless typedef.
llvm-svn: 100268
2010-04-03 04:45:24 +00:00
Johnny Chen dbdd3f8b09 Move variable "Bits" declaration/definition into the DEBUG block where its usage
is expected.

llvm-svn: 100247
2010-04-02 23:13:52 +00:00
Johnny Chen 7d363b63fd Fixed build warning.
llvm-svn: 100244
2010-04-02 22:51:04 +00:00
Johnny Chen 88a7b5a724 Change from .../Support/DataTypes.h to .../System/DataTypes.h.
(Fix build failure)

llvm-svn: 100243
2010-04-02 22:41:06 +00:00
Johnny Chen 7b999ea7b7 Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgen
backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb,
and the disassembler core which invokes the decoder function and builds up the
MCInst based on the decoded Opcode.

Reviewed by Chris Latter and Bob Wilson.

llvm-svn: 100233
2010-04-02 22:27:38 +00:00