6e7ca24907
Remove DBG_VALUE which reference dead stack slots.
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llvm-svn: 102654
2010-04-29 18:51:00 +00:00
a46953d281
DO not push DBG_VALUE machine instructions for inlined fuction arguments in entry block.
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llvm-svn: 102653
2010-04-29 18:50:36 +00:00
76d6217906
Verify metadata harder. In particular, check that module
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level metadata does not have any function local operands.
This would have caught the problem found in PR6112.
llvm-svn: 102620
2010-04-29 16:10:30 +00:00
5c864b42b2
Add comment.
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llvm-svn: 102606
2010-04-29 06:58:53 +00:00
923679f929
Re-enable 102565 with fixes.
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llvm-svn: 102602
2010-04-29 06:33:38 +00:00
38dfa5cf20
Load folding tail call should not use ebp / rbp after it's popped. PEI
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should use esp / rsp to reference frame instead.
llvm-svn: 102596
2010-04-29 05:08:22 +00:00
b0a0a26df1
Add support for assemblers that don't support periods in a name
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llvm-svn: 102594
2010-04-29 04:00:56 +00:00
d65a1e782b
Temporarily disable my changes to unbreak the build.
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llvm-svn: 102590
2010-04-29 03:34:19 +00:00
5fb45a2b85
Do not generate duplicate dbg_value instructions for function arguments.
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llvm-svn: 102585
2010-04-29 01:40:30 +00:00
d9e7322c9a
Fix missing #include.
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llvm-svn: 102584
2010-04-29 01:39:13 +00:00
70a0145d7c
Avoid emitting a dbg_value machineinstr that's not going to be inserted into entry block.
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llvm-svn: 102581
2010-04-29 01:23:55 +00:00
250e917e9d
Frame index can be negative.
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llvm-svn: 102577
2010-04-29 01:13:30 +00:00
f4336ebb2a
Check Reg against zero.
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llvm-svn: 102573
2010-04-29 00:59:34 +00:00
a5a8f76cea
- Really preserve dbg_value instructions when the register is spilled.
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- Also, update dbg_value is the value is being re-matted from a frame slot, e.g. fixed slots for arguments.
llvm-svn: 102565
2010-04-28 23:52:26 +00:00
bb728e17d3
tidy up.
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llvm-svn: 102558
2010-04-28 23:24:13 +00:00
4822841b82
Fixed the word sized Bit Scan Forward/Reverse instructions, they needed the
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Operand size override prefix to be part of their records.
llvm-svn: 102556
2010-04-28 23:20:40 +00:00
6e822459ed
Replace r102368 with code that's less fragile. This creates DBG_VALUE instructions for function arguments early and insert them after instruction selection is done.
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llvm-svn: 102554
2010-04-28 23:08:54 +00:00
04cbcca319
Add sizes non-floating point versions for the eh sjlj intrinsic expansions.
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rdar://7895451
llvm-svn: 102526
2010-04-28 20:33:09 +00:00
450e29cb4c
fix PR6112 - When globalopt (or any other pass) does RAUW(@G, %G),
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metadata references in non-function-local MDNodes should drop to
null.
llvm-svn: 102519
2010-04-28 20:16:12 +00:00
d4d1a51895
Pretty print DBG_VALUE machine instructions.
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Before:
DBG_VALUE %RSI, 0, !-1; dbg:SimpleRegisterCoalescing.cpp:2707
Now:
DBG_VALUE %RSI, 0, !"this"; dbg:SimpleRegisterCoalescing.cpp:2707
llvm-svn: 102518
2010-04-28 20:03:13 +00:00
08e9e72fa9
Rework global alignment computation again. Now we do round up
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alignment of globals to the preferred alignment, but only when
there is no section specified on the global (by far the common
case).
llvm-svn: 102515
2010-04-28 19:58:07 +00:00
888c17073a
While lowering dbg_declare, emit DBG_VALUE machine instruction if alloca matching llvm.dbg.declare intrinsic is missing.
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llvm-svn: 102513
2010-04-28 19:27:33 +00:00
06e7242d32
Recompute kill flags from live intervals after coalescing instead of trying to
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update them. Computing kill flags is notoriously difficult, and the coalescer
would get it wrong sometimes, and it would completely skip physical registers.
Now we simply remove kill flags based on the live intervals after coalescing.
This is a few percent slower, but now we get correct kill flags for physical
registers after coalescing.
llvm-svn: 102510
2010-04-28 18:28:39 +00:00
96fad31694
Teach X86FloatingPoint that a register can be killed multiple times by the same
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instruction.
This instruction would crash the pass:
INLINEASM <es:foo $0 $1>, 9, %FP0<kill>, 9, %FP0<kill>, 14, %EFLAGS<earlyclobber,def,dead>
Now it doesn't.
llvm-svn: 102509
2010-04-28 18:28:37 +00:00
050df1b8de
Enable i16 to i32 promotion by default.
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llvm-svn: 102493
2010-04-28 08:30:49 +00:00
f100557c9a
Try operation promotion only if regular dag combine and target-specific ones failed to do anything.
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llvm-svn: 102492
2010-04-28 07:10:39 +00:00
d21f564543
Unbreak the build. Only form shld / shrd after legalization.
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llvm-svn: 102488
2010-04-28 02:25:18 +00:00
50c9431203
Emit debug info for byval parameters.
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llvm-svn: 102486
2010-04-28 01:39:28 +00:00
347e3b8f15
Rather than having a ton of patterns for double shift instructions, e.g. SHLD16rrCL, just perform custom dag combine to form x86 specific dag so they match to the same pattern. This also makes sure later dag combine do not cause isel to miss them (e.g. promoting i16 to i32).
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llvm-svn: 102485
2010-04-28 01:18:01 +00:00
a3facc5cb5
further simplify EmitAlignment by eliminating the
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ForcedAlignBits argument, tweaking the single client of it.
llvm-svn: 102484
2010-04-28 01:08:40 +00:00
72bdee4c10
remove a dead argument to EmitAlignment.
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llvm-svn: 102483
2010-04-28 01:06:02 +00:00
9e06e53fc6
remove some default arguments to EmitAlignment.
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llvm-svn: 102482
2010-04-28 01:05:45 +00:00
173b2b9d05
Refactor.
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llvm-svn: 102481
2010-04-28 01:03:09 +00:00
c0458f1a40
Tweak x86 INC/DEC generation to look for CopyToReg or SETCC. Radar 7866163.
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llvm-svn: 102477
2010-04-28 00:35:10 +00:00
4bd85e47bf
further clarify alignment of globals, fix instcombine
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to not increase the alignment of globals with an assigned
alignment and section.
llvm-svn: 102476
2010-04-28 00:31:12 +00:00
12f6855f85
Use MachineOperand::is* predicates.
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llvm-svn: 102472
2010-04-27 22:24:37 +00:00
cfc76fdaf1
Use isReg(), isImm() and isFPImm().
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llvm-svn: 102470
2010-04-27 22:04:41 +00:00
1f34c2727d
Check operand type first.
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llvm-svn: 102468
2010-04-27 21:49:04 +00:00
9e3a4ef089
Fix obvious typos.
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llvm-svn: 102467
2010-04-27 21:46:03 +00:00
1a0bbe25e3
Ignore DBG_VALUE instructions that points to undef values.
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llvm-svn: 102463
2010-04-27 20:54:45 +00:00
3b928af28f
SRA promotion is also not free.
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llvm-svn: 102456
2010-04-27 19:48:31 +00:00
e813690b7a
- When legal, promote a load to zextload rather than ext load.
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- Catch more further dag combine opportunities as result of operand promotion, e.g. (i32 anyext (i16 trunc (i32 x))) -> (i32 x)
llvm-svn: 102455
2010-04-27 19:48:13 +00:00
6c74a872a8
Identify when a lexical scope is split in to multiple instruction ranges. Emit such ranges using DW_AT_ranges.
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This patch fixes bug (PR6894) introduced by previous version of this patch.
llvm-svn: 102454
2010-04-27 19:46:33 +00:00
eb828b6391
Do not count kill, implicit_def instructions as printed instructions.
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llvm-svn: 102453
2010-04-27 19:38:45 +00:00
64d43d80be
round zero-byte .zerofill directives up to 1 byte. This
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should fix some "g++.dg-struct-layout-1" failures,
rdar://7886017
llvm-svn: 102421
2010-04-27 07:41:44 +00:00
eb61a7d616
Revert a small part of 102372; this fixes at least one
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of the dbg testsuite regressions. I don't think this is
really the right fix; this change exposed an existing problem
upstream somewhere.
llvm-svn: 102410
2010-04-27 02:10:05 +00:00
44a27efdf9
Fix a problem that lower invoke has with allocas (PR6694), and
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add a version of createLowerInvokePass that allows the client
to specify whether it wants "expensive" or "cheap" lowering.
Patch by Alex Mac!
llvm-svn: 102402
2010-04-26 23:49:32 +00:00
3af635a296
add a comment in verbose-asm mode indicating why a noop is being generated.
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llvm-svn: 102401
2010-04-26 23:41:43 +00:00
6a5e706e3c
on darwin empty functions need to codegen into something of non-zero length,
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otherwise labels get incorrectly merged. We handled this by emitting a
".byte 0", but this isn't correct on thumb/arm targets where the text segment
needs to be a multiple of 2/4 bytes. Handle this by emitting a noop. This
is more gross than it should be because arm/ppc are not fully mc'ized yet.
This fixes rdar://7908505
llvm-svn: 102400
2010-04-26 23:37:21 +00:00
25f85947a3
Handle register-to-register copies within the tGPR class.
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Radar 7896289
llvm-svn: 102396
2010-04-26 23:20:08 +00:00
Evan Cheng