Commit Graph

7039 Commits

Author SHA1 Message Date
Dan Gohman 7ccc52f131 Support vector casts in more places, fixing a variety of assertion
failures.

To support this, add some utility functions to Type to help support
vector/scalar-independent code. Change ConstantInt::get and
ConstantFP::get to support vector types, and add an overload to
ConstantInt::get that uses a static IntegerType type, for
convenience.

Introduce a new getConstant method for ScalarEvolution, to simplify
common use cases.

llvm-svn: 73431
2009-06-15 22:12:54 +00:00
Devang Patel 56e6fe1642 Gracefully handle imbalanced inline function begin and end markers.
llvm-svn: 73426
2009-06-15 21:45:50 +00:00
Evan Cheng b9bff5880a ifcvt should ignore cfg where true and false successors are the same.
llvm-svn: 73423
2009-06-15 21:24:34 +00:00
Dale Johannesen 9df78ee1ae Fix the crash in this test. This is basically the same
problem addressed in 31284, but the patch there only
addressed the case where an invoke is the first thing in
a block.

llvm-svn: 73416
2009-06-15 20:59:27 +00:00
Bill Wendling 20f0adfc0e This test is failing. Revert for now.
llvm-svn: 73404
2009-06-15 19:10:56 +00:00
Bill Wendling 66e104cd11 Add another testcase for r71478.
llvm-svn: 73399
2009-06-15 18:36:34 +00:00
Arnold Schwaighofer cb9046cfc8 CheckTailCallReturnConstraints is missing a check on the
incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.

llvm-svn: 73387
2009-06-15 14:43:36 +00:00
Evan Cheng 1283c6a066 Part 1.
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.

Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0

If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.

- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.

This is work in progress, not yet enabled.

llvm-svn: 73381
2009-06-15 08:28:29 +00:00
Chris Lattner 1c0db34815 fix testcase to properly check for the patch in r73195.
llvm-svn: 73380
2009-06-15 05:46:02 +00:00
Dan Gohman 038d02e74e Implement more aggressive folding of add operand lists when
they contain multiplications of constants with add operations.
This helps simplify several kinds of things; in particular it
helps simplify expressions like ((-1 * (%a + %b)) + %a) to %b,
as expressions like this often come up in loop trip count
computations.

llvm-svn: 73361
2009-06-14 22:58:51 +00:00
Duncan Sands b6495b26e5 Testcase for PR4332.
llvm-svn: 73353
2009-06-14 22:22:42 +00:00
Dan Gohman 426901aa19 Teach SCEVExpander's visitAddRecExpr to reuse an existing canonical
induction variable when the addrec to be expanded does not require
a wider type. This eliminates the need for IndVarSimplify to
micro-manage SCEV expansions, because SCEVExpander now
automatically expands them in the form that IndVarSimplify considers
to be canonical. (LSR still micro-manages its SCEV expansions,
because it's optimizing for the target, rather than for
other optimizations.)

Also, this uses the new getAnyExtendExpr, which has more clever
expression simplification logic than the IndVarSimplify code it
replaces, and this cleans up some ugly expansions in code such as
the included masked-iv.ll testcase.

llvm-svn: 73294
2009-06-13 16:25:49 +00:00
Evan Cheng 185c9ef0a2 Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.

This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.

llvm-svn: 73291
2009-06-13 09:12:55 +00:00
Devang Patel 64e6529e76 llvm.dbg.region.end() intrinsic is not required to be in _last_ basic block in a function. If that happens then any basic block that follows (lexically) the block with regin.end will not have scope info available. LexicalScopeStack relies on processing basic block in CFG order, but this processing order is not guaranteed. Things get complicated when the optimizer gets a chance to optimizer IR with dbg intrinsics.
Apply defensive patch to preserve at least one lexical scope till the end of function.

llvm-svn: 73282
2009-06-13 02:16:18 +00:00
Dan Gohman 32cbbec335 Adjust this test's regex strings so that they work regardless
of the target's pointer size. This avoids the need for -m32 on
the llvm-gcc command-line, which some targets may not support.

llvm-svn: 73270
2009-06-12 23:31:14 +00:00
Dan Gohman 9fd76cc19c Add -m32 to llvm-gcc commands, so that this test behaves as expected
on systems which default to a 64-bit target.

llvm-svn: 73265
2009-06-12 23:02:02 +00:00
Evan Cheng b6cf8dbb96 If killed register is defined by implicit_def, do not clear it since it's live range may overlap another def of same register.
llvm-svn: 73255
2009-06-12 21:34:26 +00:00
Evan Cheng d93b5b672f Mark some pattern-less instructions as neverHasSideEffects.
llvm-svn: 73252
2009-06-12 20:46:18 +00:00
Devang Patel c1fee72162 Clear AbstractInstanceRootMap at the end of the function.
llvm-svn: 73244
2009-06-12 19:24:05 +00:00
Dan Gohman 9377b086f5 Don't do (x - (y - z)) --> (x + (z - y)) on floating-point types, because
it may round differently. This fixes PR4374.

llvm-svn: 73243
2009-06-12 19:23:25 +00:00
Dale Johannesen 9ebb4d2127 Testcase for llvm-gcc patch 73238.
llvm-svn: 73239
2009-06-12 18:41:53 +00:00
Arnold Schwaighofer e3a018d707 Fix Bug 4278: X86-64 with -tailcallopt calling convention
out of sync with regular cc.

The only difference between the tail call cc and the normal
cc was that one parameter register - R9 - was reserved for
calling functions through a function pointer. After time the
tail call cc has gotten out of sync with the regular cc. 

We can use R11 which is also caller saved but not used as
parameter register for potential function pointers and
remove the special tail call cc on x86-64.

llvm-svn: 73233
2009-06-12 16:26:57 +00:00
Nick Lewycky 25675ac14a Given two identical weak functions, produce one internal function and two weak
thunks.

llvm-svn: 73230
2009-06-12 15:56:56 +00:00
Nick Lewycky 42ded7042c This test is wrong. If you have two weak functions F and G you can't make
either one call the other since either one can be replaced at link time, and
they need to be independent.

llvm-svn: 73225
2009-06-12 13:24:41 +00:00
Nick Lewycky cf4e1dff31 Fix regular expression.
llvm-svn: 73221
2009-06-12 05:39:02 +00:00
Nick Lewycky a879819918 Don't remove aggregate-typed module level constants before encoding functions
since functions may contain aggregate constants too.

llvm-svn: 73220
2009-06-12 05:20:12 +00:00
Nick Lewycky e68347bde5 In an XFAIL line, treat "XFAIL: foo*bar" as a regular expression to be matched
against the target triple, instead of equivalent to "XFAIL: *".

llvm-svn: 73219
2009-06-12 05:18:32 +00:00
Nick Lewycky 225ab16b07 XFAIL this on PPC Linux. This keeps showing up in the buildbot and isn't easy to fix, and I'd like it to stop masking
real failures.

llvm-svn: 73211
2009-06-11 23:43:02 +00:00
Dale Johannesen 4bd5463617 Test for rev 73205 (PR 4349)
llvm-svn: 73206
2009-06-11 20:48:09 +00:00
Chris Lattner 61797e3291 Fix 4366: store to null in non-default addr space should not be
turned into unreachable.

llvm-svn: 73195
2009-06-11 17:54:56 +00:00
Daniel Dunbar 92c10927f7 Remove empty test (my DejaGNU doesn't like this)
llvm-svn: 73148
2009-06-09 21:24:39 +00:00
Bill Wendling cb61314f0f Remove empty file.
llvm-svn: 73140
2009-06-09 18:55:39 +00:00
David Greene 58a6b76cfd Revert 73074 and 73099 because Windows doesn't have POSIX
regular expressions.  We will add an OpenBSD implementation
and re-apply ASAP.

llvm-svn: 73138
2009-06-09 18:31:17 +00:00
David Greene 67c05bff31 Add a !patsubst operator. Use on string types.
llvm-svn: 73099
2009-06-08 23:05:37 +00:00
Anton Korobeynikov c745132865 Add testcase for register scanveger assertion fix in r72755
(double def due to livevars)

llvm-svn: 73096
2009-06-08 22:54:15 +00:00
David Greene 0574ff5639 Add a more robust !if test.
llvm-svn: 73091
2009-06-08 22:34:57 +00:00
David Greene bf02c8869a Fix DejaGNU run line to escape special characters.
llvm-svn: 73090
2009-06-08 22:20:58 +00:00
David Greene 8618f95caf Make IntInits and ListInits typed. This helps deduce types of !if and
other operators.  For the rare cases where a list type cannot be
deduced, provide a []<type> syntax, where <type> is the list element
type.

llvm-svn: 73078
2009-06-08 20:23:18 +00:00
David Greene 07eba05a61 Add a !regmatch operator to do pattern matching in TableGen.
llvm-svn: 73074
2009-06-08 17:00:34 +00:00
Eli Friedman 0b387fbd1b Fix the run-line for this test to work correctly outside of x86.
llvm-svn: 73025
2009-06-07 09:44:19 +00:00
Eli Friedman 516479d6e7 Tweak the expansion code for BIT_CONVERT to generate better code
converting from an MMX vector to an i64.

llvm-svn: 73024
2009-06-07 09:41:57 +00:00
Eli Friedman 3234587213 Slightly generalize the code that handles shuffles of consecutive loads
on x86 to handle more cases.  Fix a bug in said code that would cause it 
to read past the end of an object.  Rewrite the code in 
SelectionDAGLegalize::ExpandBUILD_VECTOR to be a bit more general. 
Remove PerformBuildVectorCombine, which is no longer necessary with 
these changes.  In addition to simplifying the code, with this change, 
we can now catch a few more cases of consecutive loads.

llvm-svn: 73012
2009-06-07 06:52:44 +00:00
Eli Friedman be1bb0f8b1 PR3628: Add patterns to match SHL/SRL/SRA to the corresponding Altivec
instructions.

llvm-svn: 73009
2009-06-07 01:07:55 +00:00
Eli Friedman 73a83066d5 PR4340: Run SimplifyDemandedVectorElts on insertelement instructions;
sometimes it can find simplifications that won't be found otherwise.

llvm-svn: 73006
2009-06-06 20:08:03 +00:00
Eli Friedman c61e357aa6 Fix the expansion for CONCAT_VECTORS so that it doesn't create illegal
types.

llvm-svn: 72993
2009-06-06 07:08:26 +00:00
Eli Friedman 75c496f920 Avoid crashing on a variable-index insertelement with element type i16.
llvm-svn: 72991
2009-06-06 06:32:50 +00:00
Eli Friedman 1b1844ad1f Get rid of some bogus patterns for X86vzmovl. Don't create VZEXT_MOVL
nodes for vectors with an i16 element type.  Add an optimization for 
building a vector which is all zeros/undef except for the bottom 
element, where the bottom element is an i8 or i16.

llvm-svn: 72988
2009-06-06 06:05:10 +00:00
Eli Friedman 868bd6ab52 Fix an obvious typo.
llvm-svn: 72987
2009-06-06 05:55:37 +00:00
Eli Friedman 6c101ebfa8 Get rid of a bogus pattern that interferes with optimization.
llvm-svn: 72985
2009-06-06 04:17:04 +00:00
Eli Friedman b45e8ce69a PR2598: make sure to expand illegal forms of integer/floating-point
conversions for x86, like <2 x i32> -> <2 x float> and <4 x i16> -> 
<4 x float>.

llvm-svn: 72983
2009-06-06 03:57:58 +00:00