failures.
To support this, add some utility functions to Type to help support
vector/scalar-independent code. Change ConstantInt::get and
ConstantFP::get to support vector types, and add an overload to
ConstantInt::get that uses a static IntegerType type, for
convenience.
Introduce a new getConstant method for ScalarEvolution, to simplify
common use cases.
llvm-svn: 73431
that push immediate operands of 1, 2, and 4 bytes (extended to the native
register size in each case). The assembly mnemonics are "pushl" and "pushq."
One such instruction appears at the beginning of the "start" function , so this
is essential for accurate disassembly when unwinding."
Patch by Sean Callanan!
llvm-svn: 73407
specific one. The GNU one is chosen when _GNU_SOURCE is defined. g++ always
defines _GNU_SOURCE on linux platforms because glibc's headers won't compile
in C++ mode without it. The GNU strerror_r doesn't always modify the buffer
which causes empty error messages on linux.
This patch changes MakeErrMsg to use the return value of strerror_r to get
the string instead of assuming the buffer will be modified, on GLIBC.
Patch by Benjamin Kramer!
llvm-svn: 73396
incomming chain of the RETURN node. The incomming chain must
be the outgoing chain of the CALL node. This causes the
backend to identify tail calls that are not tail calls. This
patch fixes this.
llvm-svn: 73387
Look for as in the path. Doing it here instead
of llvm-gcc because llvm-gcc has nothing as
convenient as sys::Program::FindProgramByName.
llvm-svn: 73383
- Change register allocation hint to a pair of unsigned integers. The hint type is zero (which means prefer the register specified as second part of the pair) or entirely target dependent.
- Allow targets to specify alternative register allocation orders based on allocation hint.
Part 2.
- Use the register allocation hint system to implement more aggressive load / store multiple formation.
- Aggressively form LDRD / STRD. These are formed *before* register allocation. It has to be done this way to shorten live interval of base and offset registers. e.g.
v1025 = LDR v1024, 0
v1026 = LDR v1024, 0
=>
v1025,v1026 = LDRD v1024, 0
If this transformation isn't done before allocation, v1024 will overlap v1025 which means it more difficult to allocate a register pair.
- Even with the register allocation hint, it may not be possible to get the desired allocation. In that case, the post-allocation load / store multiple pass must fix the ldrd / strd instructions. They can either become ldm / stm instructions or back to a pair of ldr / str instructions.
This is work in progress, not yet enabled.
llvm-svn: 73381
ranges more similar to the console output. Consider:
#define FOO(X, Y) X/ Y
void foo(int *P, int *Q) {
FOO(P, Q);
}
Before we emitted:
t.c:4:3:{4:3-4:6}{4:3-4:6}: error: invalid operands to binary expression ('int *' and 'int *')
FOO(P, Q);
^~~~~~~~~
...
Note that while we underline the macro args that the range info just includes FOO
without its macros. This change teaches the printed ranges to include macro args
also so that we get:
t.c:4:3:{4:3-4:12}{4:3-4:12}: error: invalid operands to binary expression ('int *' and 'int *')
FOO(P, Q);
^~~~~~~~~
...
This fixes rdar://6939599
llvm-svn: 73378
Dan Gohman