Commit Graph

189614 Commits

Author SHA1 Message Date
Duncan P. N. Exon Smith 6e6428d981 Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC"
This reverts commit r225213.  It's failing on multiple buildbots [1][2].

[1]: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22032
[2]: http://lab.llvm.org:8080/green/view/Clang/job/clang-stage1-cmake-RA-incremental_check/2357/

llvm-svn: 225222
2015-01-05 23:31:51 +00:00
Duncan P. N. Exon Smith 0aa050fbf2 Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC"
This reverts commit r225212.  It's failing on multiple buildbots [1][2].

[1]: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22032
[2]: http://lab.llvm.org:8080/green/view/Clang/job/clang-stage1-cmake-RA-incremental_check/2357/

llvm-svn: 225221
2015-01-05 23:31:42 +00:00
Hal Finkel f93f56d619 [PowerPC] Fix test to pass on Darwin hosts
llvm-svn: 225220
2015-01-05 23:17:43 +00:00
Siva Chandra 89ce955a32 Make array symbol reading resilient to incomplete DWARF.
Summary:
GCC emits DW_TAG_subrange_type for static member arrays, but with no
attributes. This in turn results in wrong type/value of the array when
printing with 'target variable <array var name>'. This patch fixes this
so that the array value is printed in this format:

    (<element type> []) <array var name> = {}

Earlier, the array was being interpreted to be of its element type.

Note: This does not fix anything to do with 'expr' or 'p' commands.
Those commands still error out complaining about incomplete types.

Test Plan: dotest.py -p TestStaticVariables

Reviewers: emaste, clayborg

Reviewed By: clayborg

Subscribers: lldb-commits

Differential Revision: http://reviews.llvm.org/D6799

llvm-svn: 225219
2015-01-05 23:06:14 +00:00
Zachary Turner d1d5cc27d6 When building on Windows, copy Python27(_d).dll to the output folder.
When Python does not exist on the system path, LLDB will be unable
to load it.  Fix this by copying the dll to the output folder so
it will be side-by-side with lldb.exe.

llvm-svn: 225218
2015-01-05 22:29:19 +00:00
Hal Finkel 6837077fcf [PowerPC] Remove old README.txt entry
We no longer generate horrible code for the stated function:

void f(signed char *a, _Bool b, _Bool c) {
  signed char t = 0;
  if (b)  t = *a;
  if (c)  *a = t;
}

for which we now generate:

.L.f:
        andi. 5, 5, 1
        cmpldi 1, 4, 0
        li 5, 0
        beq 1, .LBB0_2
        lbz 5, 0(3)
.LBB0_2:                                # %if.end
        bclr 4, 1, 0
        stb 5, 0(3)
        blr

so we don't need the README.txt entry.

llvm-svn: 225217
2015-01-05 22:20:22 +00:00
Simon Pilgrim 4c55af6850 [X86][SSE] lowerVectorShuffleAsByteShift tidyup
Removed local isSequential predicate and use standard helper isSequentialOrUndefInRange instead.

llvm-svn: 225216
2015-01-05 22:08:48 +00:00
Saleem Abdulrasool 6e6c1c3ef2 tests: correct builtins test if built under -mthumb on ARM
The clear_cache and enable_execute_stack tests attempt to memcpy the definition
of a function into a buffer before executing the function.  The problem with
this approach is that on some targets (ARM with thumb mode compilation, MIPS
with MIPS16 codegen or uMIPS), you would use a pointer which is incorrect (it
would be off-by-one) due to the ISA selection being encoded into the address.
This ensures that the function address is retrieved correctly in all cases.

llvm-svn: 225215
2015-01-05 21:54:50 +00:00
Hal Finkel 9187711f08 [PowerPC] Convert a README.txt entry into a better test
We now produce the desired code as noted in the README.txt file (no spurious
or). Remove the README entry and improve the regression test.

llvm-svn: 225214
2015-01-05 21:53:52 +00:00
Brad Smith 9cf1e26201 Use the integrated assembler by default on 32-bit PowerPC and SPARC
llvm-svn: 225213
2015-01-05 21:48:16 +00:00
Brad Smith a2e3e368e7 Use the integrated assembler by default on 32-bit PowerPC and SPARC
llvm-svn: 225212
2015-01-05 21:44:15 +00:00
Hal Finkel f4044b02a5 [PowerPC] Remove README.txt entry
This entry has been rendered irrelevant now that we have proper CR bit
tracking.

llvm-svn: 225211
2015-01-05 21:41:26 +00:00
Colin LeMahieu dacf057bdc [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references.
llvm-svn: 225210
2015-01-05 21:36:38 +00:00
Hal Finkel c7d35bb5b1 [PowerPC] Add a test for truncating a shifted load
We now produce the desired code as noted in the README.txt file. Remove the
README entry and add a regression test.

llvm-svn: 225209
2015-01-05 21:33:14 +00:00
Frederic Riss e541e0b327 Make DIE.h a public CodeGen header.
dsymutil would like to use all the AsmPrinter/MCStreamer infrastructure
to stream out the DWARF. In order to do so, it will reuse the DIE object
and so this header needs to be public.

The interface exposed here has some corners that cannot be used without a
DwarfDebug object, but clients that want to stream Dwarf can just avoid
these.

Differential Revision: http://reviews.llvm.org/D6695

llvm-svn: 225208
2015-01-05 21:29:41 +00:00
Frederic Riss 4398850779 [dsymutil] Implement the BinaryHolder object and gain archive support.
This object is meant to own the ObjectFiles and their underlying
MemoryBuffer. It is basically the equivalent of an OwningBinary
except that it efficiently handles Archives. It is optimized for
efficiently providing mappings of members of the same archive when
they are opened successively (which is standard in Darwin debug
maps, objects from the same archive will be contiguous).

Of course, the BinaryHolder will also be used by the DWARF linker
once it is commited, but for now only the debug map parser uses it.

With this change, you can run llvm-dsymutil on your Darwin debug build
of clang and get a complete debug map for it.

Differential Revision: http://reviews.llvm.org/D6690

llvm-svn: 225207
2015-01-05 21:29:28 +00:00
NAKAMURA Takumi 2997dbff12 [autoconf] llvm/cmake/modules/Makefile: Make sure to regenerate LLVMConfig.cmake whenever Makefile is updated.
llvm-svn: 225206
2015-01-05 21:24:36 +00:00
Hal Finkel a4750dec99 [PowerPC] Add another test for load/store with update
We now produce the desired code as noted in the README.txt file. Remove the
README entry and add a regression test.

llvm-svn: 225205
2015-01-05 21:22:42 +00:00
NAKAMURA Takumi 96050a8cb4 [autoconf] Export LLVM_LIBDIR_SUFFIX with empty string in LLVMConfig.cmake. tools/llvm-config is also doing so.
llvm-svn: 225204
2015-01-05 21:14:14 +00:00
Hal Finkel 200d2ad188 [PowerPC] Fold i1 extensions with other ops
Consider this function from our README.txt file:

  int foo(int a, int b) { return (a < b) << 4; }

We now explicitly track CR bits by default, so the comment in the README.txt
about not really having a SETCC is no longer accurate, but we did generate this
somewhat silly code:

        cmpw 0, 3, 4
        li 3, 0
        li 12, 1
        isel 3, 12, 3, 0
        sldi 3, 3, 4
        blr

which generates the zext as a select between 0 and 1, and then shifts the
result by a constant amount. Here we preprocess the DAG in order to fold the
results of operations on an extension of an i1 value into the SELECT_I[48]
pseudo instruction when the resulting constant can be materialized using one
instruction (just like the 0 and 1). This was not implemented as a DAGCombine
because the resulting code would have been anti-canonical and depends on
replacing chained user nodes, which does not fit well into the lowering
paradigm. Now we generate:

        cmpw 0, 3, 4
        li 3, 0
        li 12, 16
        isel 3, 12, 3, 0
        blr

which is less silly.

llvm-svn: 225203
2015-01-05 21:10:24 +00:00
Simon Pilgrim 71b96b35e1 [X86][SSE] Fixed description for isSequentialOrUndefInRange. NFC.
llvm-svn: 225202
2015-01-05 21:09:48 +00:00
Colin LeMahieu 28bb02a8c7 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts.
llvm-svn: 225201
2015-01-05 20:56:41 +00:00
Duncan P. N. Exon Smith 1c00c9f7fc IR: Prune arguments to ValueAsMetadata::ValueAsMetadata()
`LLVMContext` isn't actually used.

llvm-svn: 225200
2015-01-05 20:41:25 +00:00
Colin LeMahieu abdf2b37d8 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits.
llvm-svn: 225199
2015-01-05 20:35:54 +00:00
Colin LeMahieu 3acfddd6b5 [Hexagon] Adding V4 logic-logic instructions and tests.
llvm-svn: 225198
2015-01-05 20:14:58 +00:00
Colin LeMahieu ff10c8c95c [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions.
llvm-svn: 225197
2015-01-05 20:04:40 +00:00
Francisco Lopes da Silva 37e8f2d6a7 Fix lit for builds under /opt
llvm-svn: 225196
2015-01-05 19:59:24 +00:00
Zachary Turner f6896b09b4 Fix about 20 tests on Windows.
Passing the argument string from dosep to dotest was failing on
Windows due to the fact that Windows uses \ for its path separator.
As a result, shlex.split() was treating it as an escape character.
This fixes the issue by telling shlex.split() to not use posix mode
when running on Windows.

llvm-svn: 225195
2015-01-05 19:37:03 +00:00
Dan Albert 502b7b4b36 Fix some formatting I messed up in r225187.
llvm-svn: 225194
2015-01-05 19:31:59 +00:00
Greg Clayton a05569b0b3 Make sure x7 and x8 are treated as argument registers for arm64.
llvm-svn: 225193
2015-01-05 19:23:33 +00:00
Hal Finkel 49557f1b42 [PowerPC] Remove zexts after i32 ctlz
The 64-bit semantics of cntlzw are not special, the 32-bit population count is
stored as a 64-bit value in the range [0,32]. As a result, it is always zero
extended, and it can be added to the PPCISelDAGToDAG peephole optimization as a
frontier instruction for the removal of unnecessary zero extensions.

llvm-svn: 225192
2015-01-05 18:52:29 +00:00
Rafael Espindola 58d4c5a9c0 Make this test a bit stricter.
The first function is named __cxx_global_var_init, which is a substring of
the following functions @__cxx_global_var_init(1,2,3,etc).

llvm-svn: 225191
2015-01-05 18:48:18 +00:00
Rafael Espindola 6f39d8525c Disable warnings in this test.
This makes it a lot easier to read the output from FileCheck when it fails.

llvm-svn: 225190
2015-01-05 18:19:35 +00:00
Hal Finkel 4e2c78228a [PowerPC] Remove zexts after byte-swapping loads
lhbrx and lwbrx not only load their data with byte swapping, but also clear the
upper 32 bits (at least). As a result, they can be added to the PPCISelDAGToDAG
peephole optimization as frontier instructions for the removal of unnecessary
zero extensions.

llvm-svn: 225189
2015-01-05 18:09:06 +00:00
Colin LeMahieu 5e079577e1 [Hexagon] Adding round reg/imm and bitsplit instructions.
llvm-svn: 225188
2015-01-05 18:08:21 +00:00
Dan Albert 51477ad1a0 Make the Unwinder -Werror clean.
Mostly just format string fixes.
Tested clean on arm, x86, and x86_64 Linux.

llvm-svn: 225187
2015-01-05 18:07:36 +00:00
Saleem Abdulrasool 150a1dc5c2 SymbolRewriter: use iplist::splice
The swap implementation for iplist is currently unsupported.  Simply splice the
old list into place, which achieves the same purpose.  This is needed in order
to thread the -frewrite-map-file frontend option correctly.  NFC.

llvm-svn: 225186
2015-01-05 17:56:32 +00:00
Saleem Abdulrasool d37ce30888 SymbolRewriter: 80-column
Wrap a couple of lines.  NFC.

llvm-svn: 225185
2015-01-05 17:56:29 +00:00
Vince Harron 8cd9a47b59 fix cross compilation to 32 bit arm targets
llvm-svn: 225184
2015-01-05 17:49:23 +00:00
Ahmed Bougacha d54c448d34 [AArch64] Improve codegen of store lane instructions by avoiding GPR usage.
We used to generate code similar to:

  umov.b        w8, v0[2]
  strb  w8, [x0, x1]

because the STR*ro* patterns were preferred to ST1*.
Instead, we can avoid going through GPRs, and generate:

  add   x8, x0, x1
  st1.b { v0 }[2], [x8]

This patch increases the ST1* AddedComplexity to achieve that.

rdar://16372710
Differential Revision: http://reviews.llvm.org/D6202

llvm-svn: 225183
2015-01-05 17:10:26 +00:00
Samuel Antao 4ae1f67ccf Fix clash of gcc toolchains in driver regression tests.
For some regression tests the path to the right toolchain is specified using the -sysroot switch. However, if clang was configured with a custom gcc toolchain (either by using GCC_INSTALL_PREFIX in cmake or the equivalent configure command), the path to the custom gcc toolchain path takes precedence to the one specified by sysroot. This causes several regression tests to fail as they will be using an unexpected path. This patch fixes this issue by adding --gcc-toolchain='' to all tests that rely on that. The empty string causes the driver to pick the path from sysroot instead.

llvm-svn: 225182
2015-01-05 17:07:42 +00:00
Ahmed Bougacha f964df3640 [AArch64] Improve codegen of store lane 0 instructions by directly storing the subregister.
For 0-lane stores, we used to generate code similar to:

  fmov w8, s0
  str w8, [x0, x1, lsl #2]

instead of:

  str s0, [x0, x1, lsl #2]

To correct that: for store lane 0 patterns, directly match to STR <subreg>0.

Byte-sized instructions don't have the special case for a 0 index,
because FPR8s are defined to have untyped content.

rdar://16372710
Differential Revision: http://reviews.llvm.org/D6772

llvm-svn: 225181
2015-01-05 17:02:28 +00:00
Samuel Benzaquen 45ed4f9542 Fix dangling pointer in isDerivedFrom.
Summary:
Replace usage of StringRef with std::string in AST_MATCHER* generated
matchers to make sure they keep their own copy of the string.
The value could be a temporary and it causes the pointer to be dangling
by the time the matcher is executed.

Reviewers: klimek

Subscribers: klimek, cfe-commits

Differential Revision: http://reviews.llvm.org/D6843

llvm-svn: 225180
2015-01-05 15:26:42 +00:00
NAKAMURA Takumi f199f4c593 llvm/test/lit.cfg: have_ld_plugin_support(): Use decode() for stdout.
llvm-svn: 225171
2015-01-05 14:18:04 +00:00
NAKAMURA Takumi b0f54e7909 clang/CMakeLists.txt: Introduce LLVM_SHLIB_OUTPUT_INTDIR also here, or plugins tests might fail.
llvm-svn: 225170
2015-01-05 14:06:14 +00:00
Karthik Bhat 93f27ce886 Select lower fsub,fabs pattern to fabd on AArch64
This patch lowers patterns such as-
  fsub   v0.4s, v0.4s, v1.4s
  fabs   v0.4s, v0.4s
to
  fabd  v0.4s, v0.4s, v1.4s
on AArch64.

Review: http://reviews.llvm.org/D6791
llvm-svn: 225169
2015-01-05 13:57:59 +00:00
Rafael Espindola 7a45e8794f Fix formatting. NFC.
llvm-svn: 225168
2015-01-05 13:44:59 +00:00
Charlie Turner 6632d1f67e Parse Tag_compatibility correctly.
Tag_compatibility takes two arguments, but before this patch it would
erroneously accept just one, it now produces an error in that case.

Change-Id: I530f918587620d0d5dfebf639944d6083871ef7d
llvm-svn: 225167
2015-01-05 13:26:37 +00:00
Charlie Turner 8b2caa458f Emit the build attribute Tag_conformance.
Claim conformance to version 2.09 of the ARM ABI.

This build attribute must be emitted first amongst the build attributes when
written to an object file. This is to simplify conformance detection by
consumers.

Change-Id: If9eddcfc416bc9ad6e5cc8cdcb05d0031af7657e
llvm-svn: 225166
2015-01-05 13:12:17 +00:00
Karthik Bhat 8ec742c2f9 Select lower sub,abs pattern to sabd on AArch64
This patch lowers patterns such as-
  sub	v0.4s, v0.4s, v1.4s
  abs	v0.4s, v0.4s
to
  sabd	v0.4s, v0.4s, v1.4s
on AArch64.

Review: http://reviews.llvm.org/D6781
llvm-svn: 225165
2015-01-05 13:11:07 +00:00