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13 Commits

Author SHA1 Message Date
Evan Cheng 367a5df8cf For each instruction itinerary class, specify the number of micro-ops each 
instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.

This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.

llvm-svn: 113513
 2010-09-09 18:18:55 +00:00
Jim Grosbach 84511e1526 Clean up 80 column violations. No functional change. 
llvm-svn: 105350
 2010-06-02 21:53:11 +00:00
Anton Korobeynikov 7d62e33291 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
David Goodwin 1fd5fdaa7b Add ARMv6 itineraries. 
llvm-svn: 89218
 2009-11-18 18:39:57 +00:00
David Goodwin afcaf79603 Checkpoint NEON scheduling itineraries. 
llvm-svn: 82657
 2009-09-23 21:38:08 +00:00
David Goodwin 5090273367 Add Cortex-A8 VFP model. 
llvm-svn: 82483
 2009-09-21 20:52:17 +00:00
David Goodwin a7c2dfbca1 Update Cortex-A8 instruction itineraries for integer instructions. 
llvm-svn: 79436
 2009-08-19 18:00:44 +00:00
Evan Cheng 6ddd7bcdd1 Turn on if-conversion for thumb2. 
llvm-svn: 79084
 2009-08-15 07:59:10 +00:00
David Goodwin a9c2aad939 Finalize itineraries for cortex-a8 integer multiply 
llvm-svn: 78908
 2009-08-13 15:51:13 +00:00
David Goodwin fd5defed1d Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter. 
llvm-svn: 78736
 2009-08-11 22:38:43 +00:00
David Goodwin 62e053b790 Checkpoint scheduling itinerary changes. 
llvm-svn: 78564
 2009-08-10 15:56:13 +00:00
Evan Cheng f206d925a5 Fix comment. 
llvm-svn: 76693
 2009-07-21 23:54:22 +00:00
Evan Cheng 4e712de541 Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits. 
llvm-svn: 73747
 2009-06-19 01:51:50 +00:00