llvm-project

Commit Graph

Author	SHA1	Message	Date
Ana Pazos	05a6064385	Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237	2019-01-25 20:22:49 +00:00
Alex Bradbury	e96b7c88a3	[RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F f32 values passed on the stack would previously cause an assertion in unpackFromMemLoc.. This would only trigger in the presence of the F extension making f32 a legal type. Otherwise the f32 would be legalized. This patch fixes that by keeping LocVT=f32 when a float is passed on the stack. It also adds test coverage for this case, and tests that also demonstrate lw/sw/flw/fsw will be selected when most profitable. i.e. there is no unnecessary i32<->f32 conversion in registers. llvm-svn: 343756	2018-10-04 07:28:49 +00:00

Author

SHA1

Message

Date

Ana Pazos

05a6064385

Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI

This reapplies commit r352010 with RISC-V test fixes.

llvm-svn: 352237

2019-01-25 20:22:49 +00:00

Alex Bradbury

e96b7c88a3

[RISCV] Bugfix for floats passed on the stack with the ILP32 ABI on RV32F

f32 values passed on the stack would previously cause an assertion in 
unpackFromMemLoc.. This would only trigger in the presence of the F extension 
making f32 a legal type. Otherwise the f32 would be legalized.

This patch fixes that by keeping LocVT=f32 when a float is passed on the 
stack. It also adds test coverage for this case, and tests that also 
demonstrate lw/sw/flw/fsw will be selected when most profitable. i.e. there is 
no unnecessary i32<->f32 conversion in registers.

llvm-svn: 343756

2018-10-04 07:28:49 +00:00

2 Commits