Commit Graph

1083 Commits

Author SHA1 Message Date
Saleem Abdulrasool 6e00ca887e ARM: support tlscall relocations
This adds support for TLS CALL relocations.  TLS CALL relocations are used to
indicate to the linker to generate appropriate entries to resolve TLS references
via an appropriate function invocation (e.g. __tls_get_addr(PLT)).

In order to accomodate the linker relaxation of the TLS access model for the
references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete.
This requires that the partial inplace value is also incomplete (i.e. 0).  We
simply avoid the offset value calculation at the time of the fixup adjustment in
the ARM assembler backend.

llvm-svn: 200446
2014-01-30 04:02:31 +00:00
Renato Golin 8cea6e8fc6 Enable EHABI by default
After all hard work to implement the EHABI and with the test-suite
passing, it's time to turn it on by default and allow users to
disable it as a work-around while we fix the eventual bugs that show
up.

This commit also remove the -arm-enable-ehabi-descriptors, since we
want the tables to be printed every time the EHABI is turned on
for non-Darwin ARM targets.

Although MCJIT EHABI is not working yet (needs linking with the right
libraries), this commit also fixes some relocations on MCJIT regarding
the EH tables/lib calls, and update some tests to avoid using EH tables
when none are needed.

The EH tests in the test-suite that were previously disabled on ARM
now pass with these changes, so a follow-up commit on the test-suite
will re-enable them.

llvm-svn: 200388
2014-01-29 11:50:56 +00:00
David Woodhouse 7db3705f9e Tests for mode switching
1. test that inlineasm works
2. test that relaxable instructions are re-encoded in the correct mode.

llvm-svn: 200351
2014-01-28 23:13:30 +00:00
Mark Seaborn ba86cf51c9 ARM MC: Fix the initial DWARF CFI unwind info at the start of a function
This brings MC into line with GNU 'as' on ARM, and it brings the ARM
target into line with most other LLVM targets, which declare the
initial CFI state with addInitialFrameState().

Without this, functions generated with .cfi_startproc/endproc on ARM
will tend to cause GDB to abort with:
  gdb/dwarf2-frame.c:1132: internal-error: Unknown CFA rule.

I've also tested this by comparing the output of "readelf -w" on the
object files produced by llvm-mc and gas when given the .s file added
here.

This change is part of addressing PR18636.

Differential Revision: http://llvm-reviews.chandlerc.com/D2597

llvm-svn: 200255
2014-01-27 22:38:14 +00:00
Saleem Abdulrasool f9352a3880 MC: fix test locations/name
Placed the MC variant diagnostics in the wrong directory accidentally.  Move
them into their respective architecture specific directories.

llvm-svn: 200161
2014-01-26 22:55:02 +00:00
Saleem Abdulrasool a903661289 ARM: improve diagnostics for .word directive
If a complex expression was passed to the .word directive and the first part of
the directive failed to parse, a secondary diagnostic would be produced that
would clutter the error diagnostics.  Improve the diagnostics by consuming the
remainder of the statement.

llvm-svn: 200160
2014-01-26 22:29:50 +00:00
Artyom Skrobov eab7515385 Reverting r199886 (Prevent repetitive warnings for unrecognized processors and features)
llvm-svn: 200083
2014-01-25 16:56:18 +00:00
Alp Toker cb40291100 Fix known typos
Sweep the codebase for common typos. Includes some changes to visible function
names that were misspelt.

llvm-svn: 200018
2014-01-24 17:20:08 +00:00
Artyom Skrobov a515896343 Prevent repetitive warnings for unrecognized processors and features
llvm-svn: 199886
2014-01-23 11:31:38 +00:00
Saleem Abdulrasool 9f0a21efbb tools: support decoding ARM EHABI opcodes in readobj
Add support to llvm-readobj to decode the actual opcodes.  The ARM EHABI opcodes
are a variable length instruction set that describe the operations required for
properly unwinding stack frames.

The primary motivation for this change is to ease the creation of tests for the
ARM EHABI object emission as well as the unwinding directive handling in the ARM
IAS.

Thanks to Logan Chien for an extra test case!

llvm-svn: 199708
2014-01-21 02:33:15 +00:00
Saleem Abdulrasool d9f086036a ARM IAS: add support for .unwind_raw directive
This implements the unwind_raw directive for the ARM IAS.  The unwind_raw
directive takes the form of a stack offset value followed by one or more bytes
representing the opcodes to be emitted.  The opcode emitted will interpreted as
if it were assembled by the opcode assembler via the standard unwinding
directives.

Thanks to Logan Chien for an extra test!

llvm-svn: 199707
2014-01-21 02:33:10 +00:00
Saleem Abdulrasool 662f5c1a5a ARM IAS: support .personalityindex
The .personalityindex directive is equivalent to the .personality directive with
the ARM EABI personality with the specific index (0, 1, 2).  Both of these
directives indicate personality routines, so enhance the personality directive
handling to take into account personalityindex.

Bonus fix: flush the UnwindContext at the beginning of a new function.

Thanks to Logan Chien for additional tests!

llvm-svn: 199706
2014-01-21 02:33:02 +00:00
Kai Nacke e51c813859 ARM: add tlsldo relocation
Add support for the symbol(tlsldo) relocation. This is required in order to 
solve PR18554.

Reviewed by R. Golin, A. Korobeynikov.

llvm-svn: 199644
2014-01-20 11:00:40 +00:00
Saleem Abdulrasool 9390005577 ARM ELF: ensure that the tag types are corrected
Ensure that the tag types are reflected on a replacement.  This is particularly
important for the compatibility tag which has multiple representations where the
last definition wins.

llvm-svn: 199577
2014-01-19 08:25:41 +00:00
Saleem Abdulrasool 196c3212ba ARM: update build attributes for ABI r2.09
Update names for the names as per the current ABI errata.  Mark deprecated tags
as such.

llvm-svn: 199576
2014-01-19 08:25:35 +00:00
Benjamin Kramer dd39a98b1c ARM: Let the assembler reject v5 instructions in v4 mode.
PR18524.

llvm-svn: 199559
2014-01-18 19:03:19 +00:00
Renato Golin afc43a1cbe Add MLA alias for ARMv4 support.
Fix MLA defs to use register class GPRnopc.
Add encoding tests for multiply instructions.
(Alias for MUL/SMLAL/UMLAL added by r199026.)

Patch by Zhaoshi.

llvm-svn: 199491
2014-01-17 13:53:08 +00:00
Amara Emerson dba59eb3f4 Move the xscale build attribute test to the proper place and remove the old one.
The encoding of build attributes is already tested in CodeGen/ARM/build-attributes-encoding.s

llvm-svn: 199393
2014-01-16 15:11:54 +00:00
David Peixotto c0f92a2dc9 Fix parsing of .symver directive on ARM
ARM assembly syntax uses @ for a comment, execpt for the second
parameter of the .symver directive which requires @ as part of the
symbol name. This commit fixes the parsing of this directive by
adding a special case for ARM for this one argumnet.

To make the change we had to move the AllowAtInIdentifier variable
to the MCAsmLexer interface (from AsmLexer) and expose a setter for
the value.  The ELFAsmParser then toggles this value when parsing
the second argument to the .symver directive for a target that
uses @ as a comment symbol

llvm-svn: 199339
2014-01-15 22:40:02 +00:00
Saleem Abdulrasool bdae4b8743 ARM IAS: fix diagnostics of improper qualification
An improper qualifier would result in a superfluous error due to the parser not
consuming the remainder of the statement.  Simply consume the remainder of the
statement to avoid the error.

llvm-svn: 199035
2014-01-12 05:25:44 +00:00
Saleem Abdulrasool fb3950ec63 ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
The implicit immediate 0 forms are assembly aliases, not distinct instruction
encodings.  Fix the initial implementation introduced in r198914 to an alias to
avoid two separate instruction definitions for the same encoding.

An InstAlias is insufficient in this case as the necessary due to the need to
add a new additional operand for the implicit zero.  By using the AsmPsuedoInst,
fall back to the C++ code to transform the instruction to the equivalent
_POST_IMM form, inserting the additional implicit immediate 0.

llvm-svn: 199032
2014-01-12 04:36:01 +00:00
Joerg Sonnenberger 4bde03023b Typo
llvm-svn: 199027
2014-01-12 03:38:30 +00:00
Joerg Sonnenberger 485f00fe0f Add missing mul aliases for armv4 support. Add checks that armv4 can
assemble the various mul instructions.

llvm-svn: 199026
2014-01-12 03:35:18 +00:00
Saleem Abdulrasool 2d48edeca3 ARM IAS: support emitting constant values in target expressions
A 32-bit immediate value can be formed from a constant expression and loaded
into a register.  Add support to emit this into an object file.  Because this
value is a constant, a relocation must *not* be produced for it.

llvm-svn: 199023
2014-01-11 23:03:48 +00:00
Artyom Skrobov 4e62c0b2b2 Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M
llvm-svn: 198946
2014-01-10 16:49:49 +00:00
Artyom Skrobov 4d91d944ae Must not produce Tag_CPU_arch_profile for pre-ARMv7 cores (e.g. cortex-m0)
llvm-svn: 198945
2014-01-10 16:42:55 +00:00
Saleem Abdulrasool 435f45653a ARM IAS: support #:{lower,upper}16: for GNU compatibility
The GNU assembler supports prefixing the expression with a '#' to indiciate that
the value that is being moved is infact a constant.  This improves the
compatibility of the integrated assembler's parser for this.

llvm-svn: 198916
2014-01-10 04:38:40 +00:00
Saleem Abdulrasool e6e6d71477 ARM IAS: support GNU extension for ldrd, strd
The GNU assembler has an extension that allows for the elision of the paired
register (dt2) for the LDRD and STRD mnemonics.  Add support for this in the
assembly parser.  Canonicalise the usage during the instruction parsing from
the specified version.

llvm-svn: 198915
2014-01-10 04:38:35 +00:00
Saleem Abdulrasool 5bfefb6a8f ARM IAS: support implicit immediate 0s for {LD,ST}R{B,}T
The ARM ARM indicates the mnemonics as follows:

  ldrbt{<c>}{<q>} <Rt>, [<Rn>], {, #+/-<imm>}
  ldrt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}
  strbt{<c>}{<q>} <Rt>, [<Rn>] {, #<imm>}
  strt{<c>}{<q>} <Rt>, [<Rn>] {, #+/-<imm>}

This improves the parser to deal with the implicit immediate 0 for the mnemonics
as per the specification.

Thanks to Joerg Sonnenberger for the tests!

llvm-svn: 198914
2014-01-10 04:38:31 +00:00
Kevin Enderby 9bd296ab55 Fix a bug with the ARM thumb2 CBNZ and CBNZ instructions that
branch to the next instruction.  This can not be encoded but can be
turned into a NOP.

rdar://15062072

llvm-svn: 198904
2014-01-10 00:43:32 +00:00
Saleem Abdulrasool d88affb53c ARM IAS: properly handle expression operands
Operands which involved label arithemetic would previously fail to parse.  This
corrects that by adding the additional case for the shift operand validation.

llvm-svn: 198735
2014-01-08 03:28:14 +00:00
David Peixotto a872e0e0a6 Add ARM fconsts/fconstd aliases for vmov.f32/vmov.f64
This commit adds the pre-UAL aliases of fconsts and fconstd for
vmov.f32 and vmov.f64. They use an InstAlias rather than a
MnemonicAlias to properly support the predicate operand.

We need to support encoded 8-bit constants in order to implement the
pre-UAL fconsts/fconstd aliases for vmov.f32/vmov.f64, so this
commit also fixes parsing of encoded floating point constants used
in vmov.f32/vmov.f64 instructions. Now we can support assembly code
like this:

  fconsts s0, #0x70

which is equivalent to vmov.f32 s0, #1.0.

Most of the code was already in place to support this feature.
Previously the code was trying to accept encoded 8-bit float
constants for the vmov.f32/vmov.f64 instructions.  It looks like the
support for parsing encoded floats was lost in a refactoring in
commit r148556 and we did not have any tests in place to catch it.

The change in this commit is to keep the parsed value as a 32-bit
float instead of a 64-bit double because that is what the isFPImm()
function expects to find. There is no loss of precision by using a
32-bit float here because we are still limited to an 8-bit encoded
value in the end.

Additionally, we explicitly reject encoded 8-bit floats for
vmovf.32/64. This is the same as the current behavior, but we now do
it explicitly rather than accidently.

llvm-svn: 198697
2014-01-07 18:19:23 +00:00
Saleem Abdulrasool 4cb063cbf0 ARM IAS: allow more depth in contextual diagnostics
Switch the context to be SmallVectors.  This allows for saving additional
context when providing previous emission sites.

llvm-svn: 198665
2014-01-07 02:29:00 +00:00
Saleem Abdulrasool c493d1499a ARM IAS: refactor unwind context
Move the unwinding context for the ARM IAS into a helper class.  This is purely
a structural refactoring.  A follow up change allows for recording additional
depth to improve diagnostics.

llvm-svn: 198664
2014-01-07 02:28:55 +00:00
Saleem Abdulrasool 87ccd367b6 ARM IAS: improve .eabi_attribute handling
Parse tag names as well as expressions.  The former is part of the
specification, the latter is for improved compatibility with the GNU assembler.
Fix attribute value handling to be comformant to the specification.

llvm-svn: 198662
2014-01-07 02:28:42 +00:00
Saleem Abdulrasool 69c7caf630 MCParser: introduce Note and use it for ARM AsmParser
Introduce a new virtual method Note into the AsmParser.  This completements the
existing Warning and Error methods.  Use the new method to clean up the output
of the unwind routines in the ARM AsmParser.

llvm-svn: 198661
2014-01-07 02:28:31 +00:00
Logan Chien 05ae744813 [arm] Add softvfp to supported FPU names.
llvm-svn: 198313
2014-01-02 15:50:02 +00:00
Saleem Abdulrasool e3a9dc134d ARM IAS: account for predicated pre-UAL mnemonics
Checking the trailing letter of the mnemonic is insufficient.  Be more thorough
in the scanning of the instruction to ensure that we correctly work with the
predicated mnemonics.

llvm-svn: 198235
2013-12-30 18:38:01 +00:00
Saleem Abdulrasool 4da9c6e566 ARM: provide VFP aliases for pre-V6 mnemonics
In order to provide compatibility with the GNU assembler, provide aliases for
pre-UAL mnemonics for floating point operations.

llvm-svn: 198172
2013-12-29 17:58:35 +00:00
Joerg Sonnenberger a13f8b4f36 Recognize armv7a and friends as aliases for armv7-a etc. for the purpose
of architecture naming.

llvm-svn: 198043
2013-12-26 11:50:28 +00:00
Saleem Abdulrasool a554968dde ARM IAS: support .even directive
The .even directive aligns content to an evan-numbered address.  This is an ARM
specific directive applicable to any section.

llvm-svn: 198031
2013-12-26 01:52:28 +00:00
Saleem Abdulrasool 701875542d ARM: bkpt has an implicit immediate constant 0
The bkpt mnemonic has an implicit immediate constant of 0 unless otherwise
specified.  Add an instruction alias for the unvalued breakpoint mnemonic to
treat it as a 0.  This improves compatibility with GNU AS.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 197913
2013-12-23 17:23:58 +00:00
Saleem Abdulrasool 6e6c239e33 ARM IAS: add support for the .pool directive
The .pool directive is an alias for the .ltorg directive used to create a
literal pool.  Simply treat .pool as if .ltorg was passed.

llvm-svn: 197787
2013-12-20 07:21:16 +00:00
David Peixotto 80c083a678 Implement the .ltorg directive for ARM assembly
This directive will write out the assembler-maintained constant
pool for the current section. These constant pools are created to
support the ldr-pseudo instruction (e.g. ldr r0, =val).

The directive can be used by the programmer to place the constant
pool in a location that can be reached by a pc-relative offset in
the ldr instruction.

llvm-svn: 197711
2013-12-19 18:26:07 +00:00
David Peixotto e407d093e8 Implement the ldr-pseudo opcode for ARM assembly
The ldr-pseudo opcode is a convenience for loading 32-bit constants.
It is converted into a pc-relative load from a constant pool. For
example,

  ldr r0, =0x10001
  ldr r1, =bar

will generate this output in the final assembly

  ldr r0, .Ltmp0
  ldr r1, .Ltmp1
  ...
  .Ltmp0: .long 0x10001
  .Ltmp1: .long bar

Sketch of the LDR pseudo implementation:
  Keep a map from Section => ConstantPool

  When parsing ldr r0, =val
    parse val as an MCExpr
    get ConstantPool for current Section
    Label = CreateTempSymbol()
    remember val in ConstantPool at next free slot
    add operand to ldr that is MCSymbolRef of Label

  On finishParse() callback
    Write out all non-empty constant pools
    for each Entry in ConstantPool
      Emit Entry.Label
      Emit Entry.Value

Possible improvements to be added in a later patch:
  1. Does not convert load of small constants to mov
     (e.g. ldr r0, =0x1 => mov r0, 0x1)
  2. Does reuse constant pool entries for same constant

The implementation was tested for ARM, Thumb1, and Thumb2 targets on
linux and darwin.

llvm-svn: 197708
2013-12-19 18:12:36 +00:00
Saleem Abdulrasool c0da2cb3b4 ARM IAS: support .inst directive
This adds support for the .inst directive.  This is an ARM specific directive to
indicate an instruction encoded as a constant expression.  The major difference
between .word, .short, or .byte and .inst is that the latter will be
disassembled as an instruction since it does not get flagged as data.

llvm-svn: 197657
2013-12-19 05:17:58 +00:00
Logan Chien c4cb5d900e [arm] Pass -triple to llvm-mc for ARM ELF test cases.
Replace -arch with -triple so that we can guarantee that
ELF object files can be generated.

llvm-svn: 197062
2013-12-11 19:38:10 +00:00
Logan Chien 439e8f9e38 [arm] Implement ARM .arch directive.
llvm-svn: 197052
2013-12-11 17:16:25 +00:00
David Peixotto 2cdc56d26b Integrated assembler incorrectly lexes ARM-style comments
The integrated assembler fails to properly lex arm comments when
they are adjacent to an identifier in the input stream. The reason
is that the arm comment symbol '@' is also used as symbol variant in
other assembly languages so when lexing an identifier it allows the
'@' symbol as part of the identifier.

Example:
  $ cat comment.s
  foo:
    add r0, r0@got to parse this as a comment

  $ llvm-mc -triple armv7 comment.s
  comment.s:4:18: error: unexpected token in argument list
    add r0, r0@got to parse this as a comment
                   ^
This should be parsed as correctly as `add r0, r0`.

This commit modifes the assembly lexer to not include the '@' symbol
in identifiers when lexing for targets that use '@' for comments.

llvm-svn: 196607
2013-12-06 20:35:58 +00:00
NAKAMURA Takumi 57b20a7e54 Move llvm/test/MC/ELF/thumb-st_other.s to test/MC/ARM.
llvm-svn: 196457
2013-12-05 02:21:44 +00:00